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@@ -31,6 +31,7 @@
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#define PCI_DEVICE_ID_BRASWELL 0x2280
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#define PCI_DEVICE_ID_QUARK_X1000 0x0958
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+static struct pci_dev *mbi_pdev;
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static DEFINE_SPINLOCK(iosf_mbi_lock);
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static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
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@@ -38,8 +39,6 @@ static inline u32 iosf_mbi_form_mcr(u8 op, u8 port, u8 offset)
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return (op << 24) | (port << 16) | (offset << 8) | MBI_ENABLE;
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}
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-static struct pci_dev *mbi_pdev; /* one mbi device */
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-
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static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr)
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{
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int result;
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@@ -104,7 +103,7 @@ int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
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unsigned long flags;
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int ret;
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- /*Access to the GFX unit is handled by GPU code */
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+ /* Access to the GFX unit is handled by GPU code */
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if (port == BT_MBI_UNIT_GFX) {
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WARN_ON(1);
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return -EPERM;
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@@ -127,7 +126,7 @@ int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
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unsigned long flags;
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int ret;
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- /*Access to the GFX unit is handled by GPU code */
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+ /* Access to the GFX unit is handled by GPU code */
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if (port == BT_MBI_UNIT_GFX) {
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WARN_ON(1);
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return -EPERM;
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@@ -151,7 +150,7 @@ int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
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unsigned long flags;
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int ret;
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- /*Access to the GFX unit is handled by GPU code */
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+ /* Access to the GFX unit is handled by GPU code */
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if (port == BT_MBI_UNIT_GFX) {
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WARN_ON(1);
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return -EPERM;
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