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@@ -38,166 +38,111 @@
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#include "core.h"
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-static const struct dwc2_core_params params_hi6220 = {
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- .otg_cap = 2, /* No HNP/SRP capable */
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- .dma_desc_enable = 0,
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- .dma_desc_fs_enable = 0,
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- .speed = 0, /* High Speed */
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- .enable_dynamic_fifo = 1,
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- .en_multiple_tx_fifo = 1,
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- .host_rx_fifo_size = 512,
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- .host_nperio_tx_fifo_size = 512,
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- .host_perio_tx_fifo_size = 512,
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- .max_transfer_size = 65535,
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- .max_packet_count = 511,
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- .host_channels = 16,
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- .phy_type = 1, /* UTMI */
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- .phy_utmi_width = 8,
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- .phy_ulpi_ddr = 0, /* Single */
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- .phy_ulpi_ext_vbus = 0,
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- .i2c_enable = 0,
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- .ulpi_fs_ls = 0,
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- .host_support_fs_ls_low_power = 0,
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- .host_ls_low_power_phy_clk = 0, /* 48 MHz */
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- .ts_dline = 0,
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- .reload_ctl = 0,
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- .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
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- GAHBCFG_HBSTLEN_SHIFT,
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- .uframe_sched = 0,
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- .external_id_pin_ctl = -1,
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- .hibernation = -1,
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-};
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+static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
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+{
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+ struct dwc2_core_params *p = &hsotg->params;
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-static const struct dwc2_core_params params_bcm2835 = {
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- .otg_cap = 0, /* HNP/SRP capable */
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- .dma_desc_enable = 0,
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- .dma_desc_fs_enable = 0,
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- .speed = 0, /* High Speed */
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- .enable_dynamic_fifo = 1,
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- .en_multiple_tx_fifo = 1,
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- .host_rx_fifo_size = 774, /* 774 DWORDs */
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- .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
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- .host_perio_tx_fifo_size = 512, /* 512 DWORDs */
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- .max_transfer_size = 65535,
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- .max_packet_count = 511,
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- .host_channels = 8,
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- .phy_type = 1, /* UTMI */
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- .phy_utmi_width = 8, /* 8 bits */
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- .phy_ulpi_ddr = 0, /* Single */
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- .phy_ulpi_ext_vbus = 0,
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- .i2c_enable = 0,
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- .ulpi_fs_ls = 0,
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- .host_support_fs_ls_low_power = 0,
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- .host_ls_low_power_phy_clk = 0, /* 48 MHz */
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- .ts_dline = 0,
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- .reload_ctl = 0,
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- .ahbcfg = 0x10,
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- .uframe_sched = 0,
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- .external_id_pin_ctl = -1,
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- .hibernation = -1,
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-};
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+ p->otg_cap = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
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+ p->speed = DWC2_SPEED_PARAM_HIGH;
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+ p->host_rx_fifo_size = 774;
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+ p->host_nperio_tx_fifo_size = 256;
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+ p->host_perio_tx_fifo_size = 512;
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+ p->max_transfer_size = 65535;
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+ p->max_packet_count = 511;
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+ p->host_channels = 8;
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+ p->phy_type = 1;
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+ p->phy_utmi_width = 8;
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+ p->i2c_enable = false;
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+ p->host_ls_low_power_phy_clk = 0;
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+ p->reload_ctl = false;
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+ p->ahbcfg = 0x10;
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+ p->uframe_sched = false;
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+}
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-static const struct dwc2_core_params params_rk3066 = {
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- .otg_cap = 2, /* non-HNP/non-SRP */
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- .dma_desc_enable = 0,
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- .dma_desc_fs_enable = 0,
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- .speed = -1,
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- .enable_dynamic_fifo = 1,
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- .en_multiple_tx_fifo = -1,
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- .host_rx_fifo_size = 525, /* 525 DWORDs */
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- .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
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- .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
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- .max_transfer_size = -1,
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- .max_packet_count = -1,
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- .host_channels = -1,
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- .phy_type = -1,
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- .phy_utmi_width = -1,
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- .phy_ulpi_ddr = -1,
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- .phy_ulpi_ext_vbus = -1,
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- .i2c_enable = -1,
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- .ulpi_fs_ls = -1,
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- .host_support_fs_ls_low_power = -1,
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- .host_ls_low_power_phy_clk = -1,
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- .ts_dline = -1,
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- .reload_ctl = -1,
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- .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
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- GAHBCFG_HBSTLEN_SHIFT,
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- .uframe_sched = -1,
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- .external_id_pin_ctl = -1,
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- .hibernation = -1,
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-};
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+static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
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+{
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+ struct dwc2_core_params *p = &hsotg->params;
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-static const struct dwc2_core_params params_ltq = {
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- .otg_cap = 2, /* non-HNP/non-SRP */
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- .dma_desc_enable = -1,
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- .dma_desc_fs_enable = -1,
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- .speed = -1,
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- .enable_dynamic_fifo = -1,
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- .en_multiple_tx_fifo = -1,
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- .host_rx_fifo_size = 288, /* 288 DWORDs */
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- .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
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- .host_perio_tx_fifo_size = 96, /* 96 DWORDs */
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- .max_transfer_size = 65535,
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- .max_packet_count = 511,
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- .host_channels = -1,
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- .phy_type = -1,
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- .phy_utmi_width = -1,
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- .phy_ulpi_ddr = -1,
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- .phy_ulpi_ext_vbus = -1,
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- .i2c_enable = -1,
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- .ulpi_fs_ls = -1,
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- .host_support_fs_ls_low_power = -1,
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- .host_ls_low_power_phy_clk = -1,
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- .ts_dline = -1,
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- .reload_ctl = -1,
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- .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
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- GAHBCFG_HBSTLEN_SHIFT,
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- .uframe_sched = -1,
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- .external_id_pin_ctl = -1,
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- .hibernation = -1,
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-};
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+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
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+ p->speed = DWC2_SPEED_PARAM_HIGH;
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+ p->host_rx_fifo_size = 512;
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+ p->host_nperio_tx_fifo_size = 512;
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+ p->host_perio_tx_fifo_size = 512;
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+ p->max_transfer_size = 65535;
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+ p->max_packet_count = 511;
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+ p->host_channels = 16;
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+ p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
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+ p->phy_utmi_width = 8;
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+ p->i2c_enable = false;
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+ p->host_ls_low_power_phy_clk = 0;
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+ p->reload_ctl = false;
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+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
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+ GAHBCFG_HBSTLEN_SHIFT;
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+ p->uframe_sched = false;
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+}
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-static const struct dwc2_core_params params_amlogic = {
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- .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
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- .dma_desc_enable = 0,
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- .dma_desc_fs_enable = 0,
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- .speed = DWC2_SPEED_PARAM_HIGH,
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- .enable_dynamic_fifo = 1,
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- .en_multiple_tx_fifo = -1,
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- .host_rx_fifo_size = 512,
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- .host_nperio_tx_fifo_size = 500,
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- .host_perio_tx_fifo_size = 500,
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- .max_transfer_size = -1,
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- .max_packet_count = -1,
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- .host_channels = 16,
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- .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
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- .phy_utmi_width = -1,
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- .phy_ulpi_ddr = -1,
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- .phy_ulpi_ext_vbus = -1,
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- .i2c_enable = -1,
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- .ulpi_fs_ls = -1,
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- .host_support_fs_ls_low_power = -1,
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- .host_ls_low_power_phy_clk = -1,
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- .ts_dline = -1,
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- .reload_ctl = 1,
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- .ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
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- GAHBCFG_HBSTLEN_SHIFT,
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- .uframe_sched = 0,
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- .external_id_pin_ctl = -1,
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- .hibernation = -1,
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-};
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+static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
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+{
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+ struct dwc2_core_params *p = &hsotg->params;
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+
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+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
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+ p->host_rx_fifo_size = 525;
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+ p->host_nperio_tx_fifo_size = 128;
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+ p->host_perio_tx_fifo_size = 256;
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+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
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+ GAHBCFG_HBSTLEN_SHIFT;
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+}
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+
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+static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
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+{
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+ struct dwc2_core_params *p = &hsotg->params;
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+
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+ p->otg_cap = 2;
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+ p->host_rx_fifo_size = 288;
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+ p->host_nperio_tx_fifo_size = 128;
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+ p->host_perio_tx_fifo_size = 96;
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+ p->max_transfer_size = 65535;
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+ p->max_packet_count = 511;
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+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
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+ GAHBCFG_HBSTLEN_SHIFT;
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+}
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+
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+static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
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+{
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+ struct dwc2_core_params *p = &hsotg->params;
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+
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+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
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+ p->speed = DWC2_SPEED_PARAM_HIGH;
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+ p->host_rx_fifo_size = 512;
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+ p->host_nperio_tx_fifo_size = 500;
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+ p->host_perio_tx_fifo_size = 500;
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+ p->host_channels = 16;
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+ p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
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+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
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+ GAHBCFG_HBSTLEN_SHIFT;
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+ p->uframe_sched = false;
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+}
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+
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+static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
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+{
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+ struct dwc2_core_params *p = &hsotg->params;
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+
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+ p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
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+}
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const struct of_device_id dwc2_of_match_table[] = {
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- { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 },
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- { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 },
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- { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 },
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- { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq },
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- { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq },
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- { .compatible = "snps,dwc2", .data = NULL },
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- { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
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- { .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic },
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- { .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic },
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- { .compatible = "amcc,dwc-otg", .data = NULL },
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+ { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
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+ { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
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+ { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
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+ { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
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+ { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
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+ { .compatible = "snps,dwc2" },
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+ { .compatible = "samsung,s3c6400-hsotg" },
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+ { .compatible = "amlogic,meson8b-usb",
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+ .data = dwc2_set_amlogic_params },
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+ { .compatible = "amlogic,meson-gxbb-usb",
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+ .data = dwc2_set_amlogic_params },
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+ { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
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{},
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};
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MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
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@@ -771,9 +716,18 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
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int dwc2_init_params(struct dwc2_hsotg *hsotg)
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{
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+ const struct of_device_id *match;
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+ void (*set_params)(void *data);
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+
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dwc2_set_default_params(hsotg);
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dwc2_get_device_properties(hsotg);
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+ match = of_match_device(dwc2_of_match_table, hsotg->dev);
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+ if (match && match->data) {
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+ set_params = match->data;
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+ set_params(hsotg);
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+ }
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+
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dwc2_check_params(hsotg);
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return 0;
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