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@@ -44,7 +44,7 @@ nve0_gpio_intr(struct nouveau_subdev *subdev)
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}
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nv_wr32(priv, 0xdc00, intr0);
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- nv_wr32(priv, 0xdc88, intr1);
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+ nv_wr32(priv, 0xdc80, intr1);
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}
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void
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@@ -52,8 +52,8 @@ nve0_gpio_intr_enable(struct nouveau_event *event, int line)
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{
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const u32 addr = line < 16 ? 0xdc00 : 0xdc80;
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const u32 mask = 0x00010001 << (line & 0xf);
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- nv_wr32(event->priv, addr + 0x08, mask);
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- nv_mask(event->priv, addr + 0x00, mask, mask);
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+ nv_wr32(event->priv, addr + 0x00, mask);
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+ nv_mask(event->priv, addr + 0x08, mask, mask);
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}
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void
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@@ -61,8 +61,8 @@ nve0_gpio_intr_disable(struct nouveau_event *event, int line)
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{
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const u32 addr = line < 16 ? 0xdc00 : 0xdc80;
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const u32 mask = 0x00010001 << (line & 0xf);
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- nv_wr32(event->priv, addr + 0x08, mask);
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- nv_mask(event->priv, addr + 0x00, mask, 0x00000000);
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+ nv_mask(event->priv, addr + 0x08, mask, 0x00000000);
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+ nv_wr32(event->priv, addr + 0x00, mask);
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}
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int
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