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@@ -1150,11 +1150,19 @@
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ti,invert-autoidle-bit;
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};
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+ apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
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+ compatible = "ti,mux-clock";
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+ clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
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+ #clock-cells = <0>;
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+ reg = <0x021c 0x4>;
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+ ti,bit-shift = <7>;
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+ };
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+
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apll_pcie_ck: apll_pcie_ck {
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#clock-cells = <0>;
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- compatible = "ti,omap4-dpll-clock";
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- clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_ck>;
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- reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
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+ compatible = "ti,dra7-apll-clock";
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+ clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
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+ reg = <0x021c>, <0x0220>;
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};
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apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
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