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@@ -54,28 +54,25 @@
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/* Timer0 Timeout Counter Register */
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#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
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-static void ks8695_set_mode(enum clock_event_mode mode,
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- struct clock_event_device *evt)
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+static int ks8695_set_periodic(struct clock_event_device *evt)
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{
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+ u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
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+ u32 half = DIV_ROUND_CLOSEST(rate, 2);
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u32 tmcon;
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- if (mode == CLOCK_EVT_FEAT_PERIODIC) {
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- u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
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- u32 half = DIV_ROUND_CLOSEST(rate, 2);
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-
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- /* Disable timer 1 */
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- tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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- tmcon &= ~TMCON_T1EN;
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- writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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+ /* Disable timer 1 */
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+ tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
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+ tmcon &= ~TMCON_T1EN;
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+ writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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- /* Both registers need to count down */
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- writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
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- writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
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+ /* Both registers need to count down */
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+ writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
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+ writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
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- /* Re-enable timer1 */
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- tmcon |= TMCON_T1EN;
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- writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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- }
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+ /* Re-enable timer1 */
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+ tmcon |= TMCON_T1EN;
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+ writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
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+ return 0;
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}
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static int ks8695_set_next_event(unsigned long cycles,
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@@ -102,11 +99,13 @@ static int ks8695_set_next_event(unsigned long cycles,
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}
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static struct clock_event_device clockevent_ks8695 = {
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- .name = "ks8695_t1tc",
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- .rating = 300, /* Reasonably fast and accurate clock event */
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- .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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- .set_next_event = ks8695_set_next_event,
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- .set_mode = ks8695_set_mode,
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+ .name = "ks8695_t1tc",
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+ /* Reasonably fast and accurate clock event */
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+ .rating = 300,
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+ .features = CLOCK_EVT_FEAT_ONESHOT |
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+ CLOCK_EVT_FEAT_PERIODIC,
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+ .set_next_event = ks8695_set_next_event,
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+ .set_state_periodic = ks8695_set_periodic,
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};
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/*
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