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@@ -246,28 +246,27 @@ static void toggle_nb_mca_mst_cpu(u16 nid)
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static void prepare_msrs(void *info)
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{
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- struct mce i_mce = *(struct mce *)info;
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- u8 b = i_mce.bank;
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+ struct mce m = *(struct mce *)info;
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+ u8 b = m.bank;
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- wrmsrl(MSR_IA32_MCG_STATUS, i_mce.mcgstatus);
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+ wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
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if (boot_cpu_has(X86_FEATURE_SMCA)) {
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- if (i_mce.inject_flags == DFR_INT_INJ) {
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- wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), i_mce.status);
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- wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), i_mce.addr);
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+ if (m.inject_flags == DFR_INT_INJ) {
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+ wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status);
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+ wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr);
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} else {
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- wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), i_mce.status);
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- wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), i_mce.addr);
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+ wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status);
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+ wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr);
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}
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- wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), i_mce.misc);
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- wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), i_mce.synd);
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+ wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc);
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+ wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd);
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} else {
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- wrmsrl(MSR_IA32_MCx_STATUS(b), i_mce.status);
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- wrmsrl(MSR_IA32_MCx_ADDR(b), i_mce.addr);
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- wrmsrl(MSR_IA32_MCx_MISC(b), i_mce.misc);
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+ wrmsrl(MSR_IA32_MCx_STATUS(b), m.status);
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+ wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr);
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+ wrmsrl(MSR_IA32_MCx_MISC(b), m.misc);
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}
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-
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}
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static void do_inject(void)
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@@ -441,7 +440,7 @@ static struct dfs_node {
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static int __init init_mce_inject(void)
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{
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- int i;
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+ unsigned int i;
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u64 cap;
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rdmsrl(MSR_IA32_MCG_CAP, cap);
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