|
@@ -1540,17 +1540,7 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev,
|
|
|
|
|
|
DSSDBG("DSI PLL clock config starts");
|
|
|
|
|
|
- dsi->current_cinfo.fint = cinfo->fint;
|
|
|
- dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
|
|
|
- dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
|
|
|
- cinfo->dsi_pll_hsdiv_dispc_clk;
|
|
|
- dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
|
|
|
- cinfo->dsi_pll_hsdiv_dsi_clk;
|
|
|
-
|
|
|
- dsi->current_cinfo.regn = cinfo->regn;
|
|
|
- dsi->current_cinfo.regm = cinfo->regm;
|
|
|
- dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
|
|
|
- dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
|
|
|
+ dsi->current_cinfo = *cinfo;
|
|
|
|
|
|
DSSDBG("DSI Fint %ld\n", cinfo->fint);
|
|
|
|