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@@ -1136,7 +1136,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
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/* Use the large buffer method to calculate cursor watermark */
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line_time_us = max(htotal * 1000 / clock, 1);
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line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
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- entries = line_count * 64 * pixel_size;
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+ entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
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tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
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if (tlb_miss > 0)
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entries += tlb_miss;
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@@ -1222,7 +1222,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
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*display_wm = entries + display->guard_size;
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/* calculate the self-refresh watermark for display cursor */
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- entries = line_count * pixel_size * 64;
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+ entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
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entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
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*cursor_wm = entries + cursor->guard_size;
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@@ -1457,7 +1457,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
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entries, srwm);
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entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
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- pixel_size * 64;
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+ pixel_size * to_intel_crtc(crtc)->cursor_width;
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entries = DIV_ROUND_UP(entries,
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i965_cursor_wm_info.cacheline_size);
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cursor_sr = i965_cursor_wm_info.fifo_size -
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@@ -2120,7 +2120,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
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p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
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p->cur.bytes_per_pixel = 4;
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p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
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- p->cur.horiz_pixels = 64;
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+ p->cur.horiz_pixels = intel_crtc->cursor_width;
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/* TODO: for now, assume primary and cursor planes are always enabled. */
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p->pri.enabled = true;
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p->cur.enabled = true;
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