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@@ -4189,55 +4189,56 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
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switch (type) {
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switch (type) {
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case PP_SCLK:
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case PP_SCLK:
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- if (data->registry_data.sclk_dpm_key_disabled)
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- break;
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-
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for (i = 0; i < 32; i++) {
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for (i = 0; i < 32; i++) {
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if (mask & (1 << i))
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if (mask & (1 << i))
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break;
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break;
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}
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}
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+ data->smc_state_table.gfx_boot_level = i;
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- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
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- hwmgr->smumgr,
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- PPSMC_MSG_SetSoftMinGfxclkByIndex,
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- i),
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- "Failed to set soft min sclk index!",
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- return -1);
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+ for (i = 31; i >= 0; i--) {
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+ if (mask & (1 << i))
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+ break;
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+ }
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+ data->smc_state_table.gfx_max_level = i;
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+
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+ PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
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+ "Failed to upload boot level to lowest!",
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+ return -EINVAL);
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+
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+ PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
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+ "Failed to upload dpm max level to highest!",
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+ return -EINVAL);
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break;
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break;
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case PP_MCLK:
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case PP_MCLK:
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- if (data->registry_data.mclk_dpm_key_disabled)
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- break;
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-
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for (i = 0; i < 32; i++) {
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for (i = 0; i < 32; i++) {
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if (mask & (1 << i))
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if (mask & (1 << i))
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break;
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break;
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}
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}
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- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
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- hwmgr->smumgr,
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- PPSMC_MSG_SetSoftMinUclkByIndex,
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- i),
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- "Failed to set soft min mclk index!",
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- return -1);
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- break;
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-
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- case PP_PCIE:
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- if (data->registry_data.pcie_dpm_key_disabled)
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- break;
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-
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for (i = 0; i < 32; i++) {
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for (i = 0; i < 32; i++) {
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if (mask & (1 << i))
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if (mask & (1 << i))
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break;
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break;
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}
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}
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+ data->smc_state_table.mem_boot_level = i;
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+
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+ for (i = 31; i >= 0; i--) {
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+ if (mask & (1 << i))
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+ break;
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+ }
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+ data->smc_state_table.mem_max_level = i;
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+
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+ PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
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+ "Failed to upload boot level to lowest!",
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+ return -EINVAL);
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+
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+ PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
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+ "Failed to upload dpm max level to highest!",
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+ return -EINVAL);
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- PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc_with_parameter(
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- hwmgr->smumgr,
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- PPSMC_MSG_SetMinLinkDpmByIndex,
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- i),
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- "Failed to set min pcie index!",
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- return -1);
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break;
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break;
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+
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+ case PP_PCIE:
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default:
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default:
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break;
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break;
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}
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}
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