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@@ -1230,6 +1230,7 @@ static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
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u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
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u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
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u32 set = AR_STA_ID1_KSRCH_MODE;
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u32 set = AR_STA_ID1_KSRCH_MODE;
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+ ENABLE_REG_RMW_BUFFER(ah);
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switch (opmode) {
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switch (opmode) {
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case NL80211_IFTYPE_ADHOC:
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case NL80211_IFTYPE_ADHOC:
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if (!AR_SREV_9340_13(ah)) {
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if (!AR_SREV_9340_13(ah)) {
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@@ -1251,6 +1252,7 @@ static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
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break;
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break;
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}
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}
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REG_RMW(ah, AR_STA_ID1, set, mask);
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REG_RMW(ah, AR_STA_ID1, set, mask);
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+ REG_RMW_BUFFER_FLUSH(ah);
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}
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}
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void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
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void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
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@@ -1963,6 +1965,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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if (!ath9k_hw_mci_is_enabled(ah))
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if (!ath9k_hw_mci_is_enabled(ah))
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REG_WRITE(ah, AR_OBS, 8);
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REG_WRITE(ah, AR_OBS, 8);
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+ ENABLE_REG_RMW_BUFFER(ah);
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if (ah->config.rx_intr_mitigation) {
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if (ah->config.rx_intr_mitigation) {
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REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
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REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
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REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
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REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
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@@ -1972,6 +1975,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
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REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
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REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
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REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
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REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
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}
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}
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+ REG_RMW_BUFFER_FLUSH(ah);
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ath9k_hw_init_bb(ah, chan);
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ath9k_hw_init_bb(ah, chan);
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