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@@ -1,5 +1,5 @@
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/*********************************************************************
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/*********************************************************************
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- *
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+ *
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* Filename: w83977af_ir.c
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* Filename: w83977af_ir.c
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* Version: 1.0
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* Version: 1.0
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* Description: FIR driver for the Winbond W83977AF Super I/O chip
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* Description: FIR driver for the Winbond W83977AF Super I/O chip
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@@ -8,31 +8,31 @@
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* Created at: Wed Nov 4 11:46:16 1998
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* Created at: Wed Nov 4 11:46:16 1998
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* Modified at: Fri Jan 28 12:10:59 2000
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* Modified at: Fri Jan 28 12:10:59 2000
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* Modified by: Dag Brattli <dagb@cs.uit.no>
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* Modified by: Dag Brattli <dagb@cs.uit.no>
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- *
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+ *
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* Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
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* Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
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* Copyright (c) 1998-1999 Rebel.com
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* Copyright (c) 1998-1999 Rebel.com
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License as
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- * published by the Free Software Foundation; either version 2 of
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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* the License, or (at your option) any later version.
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- *
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+ *
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* Neither Paul VanderSpek nor Rebel.com admit liability nor provide
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* Neither Paul VanderSpek nor Rebel.com admit liability nor provide
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* warranty for any of this software. This material is provided "AS-IS"
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* warranty for any of this software. This material is provided "AS-IS"
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* and at no charge.
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* and at no charge.
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- *
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+ *
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* If you find bugs in this file, its very likely that the same bug
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* If you find bugs in this file, its very likely that the same bug
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* will also be in pc87108.c since the implementations are quite
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* will also be in pc87108.c since the implementations are quite
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* similar.
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* similar.
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*
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*
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* Notice that all functions that needs to access the chip in _any_
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* Notice that all functions that needs to access the chip in _any_
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- * way, must save BSR register on entry, and restore it on exit.
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+ * way, must save BSR register on entry, and restore it on exit.
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* It is _very_ important to follow this policy!
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* It is _very_ important to follow this policy!
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*
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*
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* __u8 bank;
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* __u8 bank;
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- *
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+ *
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* bank = inb( iobase+BSR);
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* bank = inb( iobase+BSR);
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- *
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+ *
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* do_your_stuff_here();
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* do_your_stuff_here();
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*
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*
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* outb( bank, iobase+BSR);
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* outb( bank, iobase+BSR);
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@@ -63,7 +63,7 @@
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#include "w83977af_ir.h"
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#include "w83977af_ir.h"
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#define CONFIG_USE_W977_PNP /* Currently needed */
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#define CONFIG_USE_W977_PNP /* Currently needed */
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-#define PIO_MAX_SPEED 115200
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+#define PIO_MAX_SPEED 115200
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static char *driver_name = "w83977af_ir";
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static char *driver_name = "w83977af_ir";
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static int qos_mtt_bits = 0x07; /* 1 ms or more */
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static int qos_mtt_bits = 0x07; /* 1 ms or more */
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@@ -83,11 +83,11 @@ static unsigned int efio = W977_EFIO_BASE;
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static struct w83977af_ir *dev_self[] = { NULL, NULL, NULL, NULL};
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static struct w83977af_ir *dev_self[] = { NULL, NULL, NULL, NULL};
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/* Some prototypes */
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/* Some prototypes */
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-static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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+static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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unsigned int dma);
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unsigned int dma);
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static int w83977af_close(struct w83977af_ir *self);
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static int w83977af_close(struct w83977af_ir *self);
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static int w83977af_probe(int iobase, int irq, int dma);
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static int w83977af_probe(int iobase, int irq, int dma);
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-static int w83977af_dma_receive(struct w83977af_ir *self);
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+static int w83977af_dma_receive(struct w83977af_ir *self);
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static int w83977af_dma_receive_complete(struct w83977af_ir *self);
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static int w83977af_dma_receive_complete(struct w83977af_ir *self);
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static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
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static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
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struct net_device *dev);
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struct net_device *dev);
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@@ -108,7 +108,7 @@ static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd
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*/
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*/
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static int __init w83977af_init(void)
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static int __init w83977af_init(void)
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{
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{
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- int i;
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+ int i;
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for (i=0; i < ARRAY_SIZE(dev_self) && io[i] < 2000; i++) {
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for (i=0; i < ARRAY_SIZE(dev_self) && io[i] < 2000; i++) {
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if (w83977af_open(i, io[i], irq[i], dma[i]) == 0)
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if (w83977af_open(i, io[i], irq[i], dma[i]) == 0)
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@@ -150,7 +150,7 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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unsigned int dma)
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unsigned int dma)
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{
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{
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struct net_device *dev;
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struct net_device *dev;
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- struct w83977af_ir *self;
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+ struct w83977af_ir *self;
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int err;
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int err;
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/* Lock the port that we need */
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/* Lock the port that we need */
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@@ -177,18 +177,18 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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self = netdev_priv(dev);
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self = netdev_priv(dev);
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spin_lock_init(&self->lock);
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spin_lock_init(&self->lock);
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-
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+
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/* Initialize IO */
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/* Initialize IO */
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- self->io.fir_base = iobase;
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- self->io.irq = irq;
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- self->io.fir_ext = CHIP_IO_EXTENT;
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- self->io.dma = dma;
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- self->io.fifo_size = 32;
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+ self->io.fir_base = iobase;
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+ self->io.irq = irq;
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+ self->io.fir_ext = CHIP_IO_EXTENT;
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+ self->io.dma = dma;
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+ self->io.fifo_size = 32;
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/* Initialize QoS for this device */
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/* Initialize QoS for this device */
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irda_init_max_qos_capabilies(&self->qos);
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irda_init_max_qos_capabilies(&self->qos);
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-
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+
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/* The only value we must override it the baudrate */
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/* The only value we must override it the baudrate */
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/* FIXME: The HP HDLS-1100 does not support 1152000! */
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/* FIXME: The HP HDLS-1100 does not support 1152000! */
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@@ -198,11 +198,11 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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/* The HP HDLS-1100 needs 1 ms according to the specs */
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/* The HP HDLS-1100 needs 1 ms according to the specs */
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self->qos.min_turn_time.bits = qos_mtt_bits;
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self->qos.min_turn_time.bits = qos_mtt_bits;
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irda_qos_bits_to_value(&self->qos);
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irda_qos_bits_to_value(&self->qos);
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-
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+
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/* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
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/* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
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- self->rx_buff.truesize = 14384;
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+ self->rx_buff.truesize = 14384;
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self->tx_buff.truesize = 4000;
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self->tx_buff.truesize = 4000;
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-
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+
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/* Allocate memory if needed */
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/* Allocate memory if needed */
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self->rx_buff.head =
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self->rx_buff.head =
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dma_zalloc_coherent(NULL, self->rx_buff.truesize,
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dma_zalloc_coherent(NULL, self->rx_buff.truesize,
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@@ -238,12 +238,12 @@ static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
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/* Need to store self somewhere */
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/* Need to store self somewhere */
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dev_self[i] = self;
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dev_self[i] = self;
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-
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+
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return 0;
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return 0;
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err_out3:
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err_out3:
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dma_free_coherent(NULL, self->tx_buff.truesize,
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dma_free_coherent(NULL, self->tx_buff.truesize,
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self->tx_buff.head, self->tx_buff_dma);
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self->tx_buff.head, self->tx_buff_dma);
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-err_out2:
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+err_out2:
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dma_free_coherent(NULL, self->rx_buff.truesize,
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dma_free_coherent(NULL, self->rx_buff.truesize,
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self->rx_buff.head, self->rx_buff_dma);
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self->rx_buff.head, self->rx_buff_dma);
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err_out1:
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err_out1:
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@@ -288,7 +288,7 @@ static int w83977af_close(struct w83977af_ir *self)
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if (self->tx_buff.head)
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if (self->tx_buff.head)
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dma_free_coherent(NULL, self->tx_buff.truesize,
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dma_free_coherent(NULL, self->tx_buff.truesize,
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self->tx_buff.head, self->tx_buff_dma);
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self->tx_buff.head, self->tx_buff_dma);
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-
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+
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if (self->rx_buff.head)
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if (self->rx_buff.head)
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dma_free_coherent(NULL, self->rx_buff.truesize,
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dma_free_coherent(NULL, self->rx_buff.truesize,
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self->rx_buff.head, self->rx_buff_dma);
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self->rx_buff.head, self->rx_buff_dma);
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@@ -300,106 +300,106 @@ static int w83977af_close(struct w83977af_ir *self)
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static int w83977af_probe(int iobase, int irq, int dma)
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static int w83977af_probe(int iobase, int irq, int dma)
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{
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{
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- int version;
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+ int version;
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int i;
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int i;
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-
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- for (i=0; i < 2; i++) {
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+
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+ for (i=0; i < 2; i++) {
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#ifdef CONFIG_USE_W977_PNP
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#ifdef CONFIG_USE_W977_PNP
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- /* Enter PnP configuration mode */
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+ /* Enter PnP configuration mode */
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w977_efm_enter(efbase[i]);
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w977_efm_enter(efbase[i]);
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-
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- w977_select_device(W977_DEVICE_IR, efbase[i]);
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-
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- /* Configure PnP port, IRQ, and DMA channel */
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- w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]);
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- w977_write_reg(0x61, (iobase) & 0xff, efbase[i]);
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-
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- w977_write_reg(0x70, irq, efbase[i]);
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+
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+ w977_select_device(W977_DEVICE_IR, efbase[i]);
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+
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+ /* Configure PnP port, IRQ, and DMA channel */
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+ w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]);
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+ w977_write_reg(0x61, (iobase) & 0xff, efbase[i]);
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+
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+ w977_write_reg(0x70, irq, efbase[i]);
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#ifdef CONFIG_ARCH_NETWINDER
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#ifdef CONFIG_ARCH_NETWINDER
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/* Netwinder uses 1 higher than Linux */
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/* Netwinder uses 1 higher than Linux */
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- w977_write_reg(0x74, dma+1, efbase[i]);
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+ w977_write_reg(0x74, dma+1, efbase[i]);
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#else
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#else
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- w977_write_reg(0x74, dma, efbase[i]);
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+ w977_write_reg(0x74, dma, efbase[i]);
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#endif /* CONFIG_ARCH_NETWINDER */
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#endif /* CONFIG_ARCH_NETWINDER */
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- w977_write_reg(0x75, 0x04, efbase[i]); /* Disable Tx DMA */
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-
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- /* Set append hardware CRC, enable IR bank selection */
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- w977_write_reg(0xf0, APEDCRC|ENBNKSEL, efbase[i]);
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-
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- /* Activate device */
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- w977_write_reg(0x30, 0x01, efbase[i]);
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-
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- w977_efm_exit(efbase[i]);
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+ w977_write_reg(0x75, 0x04, efbase[i]);/* Disable Tx DMA */
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+
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+ /* Set append hardware CRC, enable IR bank selection */
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+ w977_write_reg(0xf0, APEDCRC | ENBNKSEL, efbase[i]);
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+
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+ /* Activate device */
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+ w977_write_reg(0x30, 0x01, efbase[i]);
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+
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+ w977_efm_exit(efbase[i]);
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#endif /* CONFIG_USE_W977_PNP */
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#endif /* CONFIG_USE_W977_PNP */
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- /* Disable Advanced mode */
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- switch_bank(iobase, SET2);
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- outb(iobase+2, 0x00);
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-
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- /* Turn on UART (global) interrupts */
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- switch_bank(iobase, SET0);
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- outb(HCR_EN_IRQ, iobase+HCR);
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-
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- /* Switch to advanced mode */
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- switch_bank(iobase, SET2);
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- outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
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-
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- /* Set default IR-mode */
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- switch_bank(iobase, SET0);
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- outb(HCR_SIR, iobase+HCR);
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-
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- /* Read the Advanced IR ID */
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- switch_bank(iobase, SET3);
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- version = inb(iobase+AUID);
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-
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- /* Should be 0x1? */
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- if (0x10 == (version & 0xf0)) {
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- efio = efbase[i];
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-
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- /* Set FIFO size to 32 */
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- switch_bank(iobase, SET2);
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- outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
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-
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- /* Set FIFO threshold to TX17, RX16 */
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- switch_bank(iobase, SET0);
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- outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST|
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+ /* Disable Advanced mode */
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+ switch_bank(iobase, SET2);
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+ outb(iobase+2, 0x00);
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+
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+ /* Turn on UART (global) interrupts */
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+ switch_bank(iobase, SET0);
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+ outb(HCR_EN_IRQ, iobase+HCR);
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+
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+ /* Switch to advanced mode */
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+ switch_bank(iobase, SET2);
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+ outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
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+
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+ /* Set default IR-mode */
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+ switch_bank(iobase, SET0);
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+ outb(HCR_SIR, iobase+HCR);
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+
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+ /* Read the Advanced IR ID */
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+ switch_bank(iobase, SET3);
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+ version = inb(iobase+AUID);
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+
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+ /* Should be 0x1? */
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+ if (0x10 == (version & 0xf0)) {
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+ efio = efbase[i];
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+
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+ /* Set FIFO size to 32 */
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+ switch_bank(iobase, SET2);
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+ outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
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+
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+ /* Set FIFO threshold to TX17, RX16 */
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+ switch_bank(iobase, SET0);
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+ outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST|
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UFR_EN_FIFO,iobase+UFR);
|
|
UFR_EN_FIFO,iobase+UFR);
|
|
-
|
|
|
|
- /* Receiver frame length */
|
|
|
|
- switch_bank(iobase, SET4);
|
|
|
|
|
|
+
|
|
|
|
+ /* Receiver frame length */
|
|
|
|
+ switch_bank(iobase, SET4);
|
|
outb(2048 & 0xff, iobase+6);
|
|
outb(2048 & 0xff, iobase+6);
|
|
outb((2048 >> 8) & 0x1f, iobase+7);
|
|
outb((2048 >> 8) & 0x1f, iobase+7);
|
|
|
|
|
|
- /*
|
|
|
|
- * Init HP HSDL-1100 transceiver.
|
|
|
|
- *
|
|
|
|
- * Set IRX_MSL since we have 2 * receive paths IRRX,
|
|
|
|
- * and IRRXH. Clear IRSL0D since we want IRSL0 * to
|
|
|
|
- * be a input pin used for IRRXH
|
|
|
|
|
|
+ /*
|
|
|
|
+ * Init HP HSDL-1100 transceiver.
|
|
*
|
|
*
|
|
- * IRRX pin 37 connected to receiver
|
|
|
|
|
|
+ * Set IRX_MSL since we have 2 * receive paths IRRX,
|
|
|
|
+ * and IRRXH. Clear IRSL0D since we want IRSL0 * to
|
|
|
|
+ * be a input pin used for IRRXH
|
|
|
|
+ *
|
|
|
|
+ * IRRX pin 37 connected to receiver
|
|
* IRTX pin 38 connected to transmitter
|
|
* IRTX pin 38 connected to transmitter
|
|
- * FIRRX pin 39 connected to receiver (IRSL0)
|
|
|
|
|
|
+ * FIRRX pin 39 connected to receiver (IRSL0)
|
|
* CIRRX pin 40 connected to pin 37
|
|
* CIRRX pin 40 connected to pin 37
|
|
*/
|
|
*/
|
|
switch_bank(iobase, SET7);
|
|
switch_bank(iobase, SET7);
|
|
outb(0x40, iobase+7);
|
|
outb(0x40, iobase+7);
|
|
-
|
|
|
|
|
|
+
|
|
net_info_ratelimited("W83977AF (IR) driver loaded. Version: 0x%02x\n",
|
|
net_info_ratelimited("W83977AF (IR) driver loaded. Version: 0x%02x\n",
|
|
version);
|
|
version);
|
|
-
|
|
|
|
|
|
+
|
|
return 0;
|
|
return 0;
|
|
} else {
|
|
} else {
|
|
/* Try next extented function register address */
|
|
/* Try next extented function register address */
|
|
pr_debug("%s(), Wrong chip version", __func__);
|
|
pr_debug("%s(), Wrong chip version", __func__);
|
|
}
|
|
}
|
|
- }
|
|
|
|
|
|
+ }
|
|
return -1;
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
|
|
static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
|
|
static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
|
|
{
|
|
{
|
|
int ir_mode = HCR_SIR;
|
|
int ir_mode = HCR_SIR;
|
|
- int iobase;
|
|
|
|
|
|
+ int iobase;
|
|
__u8 set;
|
|
__u8 set;
|
|
|
|
|
|
iobase = self->io.fir_base;
|
|
iobase = self->io.fir_base;
|
|
@@ -448,8 +448,8 @@ static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
|
|
|
|
|
|
/* set FIFO size to 32 */
|
|
/* set FIFO size to 32 */
|
|
switch_bank(iobase, SET2);
|
|
switch_bank(iobase, SET2);
|
|
- outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
|
|
|
|
-
|
|
|
|
|
|
+ outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
|
|
|
|
+
|
|
/* set FIFO threshold to TX17, RX16 */
|
|
/* set FIFO threshold to TX17, RX16 */
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
outb(0x00, iobase+UFR); /* Reset */
|
|
outb(0x00, iobase+UFR); /* Reset */
|
|
@@ -457,7 +457,7 @@ static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
|
|
outb(0xa7, iobase+UFR);
|
|
outb(0xa7, iobase+UFR);
|
|
|
|
|
|
netif_wake_queue(self->netdev);
|
|
netif_wake_queue(self->netdev);
|
|
-
|
|
|
|
|
|
+
|
|
/* Enable some interrupts so we can receive frames */
|
|
/* Enable some interrupts so we can receive frames */
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
if (speed > PIO_MAX_SPEED) {
|
|
if (speed > PIO_MAX_SPEED) {
|
|
@@ -465,7 +465,7 @@ static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
|
|
w83977af_dma_receive(self);
|
|
w83977af_dma_receive(self);
|
|
} else
|
|
} else
|
|
outb(ICR_ERBRI, iobase+ICR);
|
|
outb(ICR_ERBRI, iobase+ICR);
|
|
-
|
|
|
|
|
|
+
|
|
/* Restore SSR */
|
|
/* Restore SSR */
|
|
outb(set, iobase+SSR);
|
|
outb(set, iobase+SSR);
|
|
}
|
|
}
|
|
@@ -484,23 +484,23 @@ static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
|
|
int iobase;
|
|
int iobase;
|
|
__u8 set;
|
|
__u8 set;
|
|
int mtt;
|
|
int mtt;
|
|
-
|
|
|
|
|
|
+
|
|
self = netdev_priv(dev);
|
|
self = netdev_priv(dev);
|
|
|
|
|
|
iobase = self->io.fir_base;
|
|
iobase = self->io.fir_base;
|
|
|
|
|
|
pr_debug("%s(%ld), skb->len=%d\n", __func__ , jiffies,
|
|
pr_debug("%s(%ld), skb->len=%d\n", __func__ , jiffies,
|
|
(int)skb->len);
|
|
(int)skb->len);
|
|
-
|
|
|
|
|
|
+
|
|
/* Lock transmit buffer */
|
|
/* Lock transmit buffer */
|
|
netif_stop_queue(dev);
|
|
netif_stop_queue(dev);
|
|
-
|
|
|
|
|
|
+
|
|
/* Check if we need to change the speed */
|
|
/* Check if we need to change the speed */
|
|
speed = irda_get_next_speed(skb);
|
|
speed = irda_get_next_speed(skb);
|
|
if ((speed != self->io.speed) && (speed != -1)) {
|
|
if ((speed != self->io.speed) && (speed != -1)) {
|
|
/* Check for empty frame */
|
|
/* Check for empty frame */
|
|
if (!skb->len) {
|
|
if (!skb->len) {
|
|
- w83977af_change_speed(self, speed);
|
|
|
|
|
|
+ w83977af_change_speed(self, speed);
|
|
dev_kfree_skb(skb);
|
|
dev_kfree_skb(skb);
|
|
return NETDEV_TX_OK;
|
|
return NETDEV_TX_OK;
|
|
} else
|
|
} else
|
|
@@ -509,29 +509,29 @@ static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
|
|
|
|
|
|
/* Save current set */
|
|
/* Save current set */
|
|
set = inb(iobase+SSR);
|
|
set = inb(iobase+SSR);
|
|
-
|
|
|
|
|
|
+
|
|
/* Decide if we should use PIO or DMA transfer */
|
|
/* Decide if we should use PIO or DMA transfer */
|
|
if (self->io.speed > PIO_MAX_SPEED) {
|
|
if (self->io.speed > PIO_MAX_SPEED) {
|
|
self->tx_buff.data = self->tx_buff.head;
|
|
self->tx_buff.data = self->tx_buff.head;
|
|
skb_copy_from_linear_data(skb, self->tx_buff.data, skb->len);
|
|
skb_copy_from_linear_data(skb, self->tx_buff.data, skb->len);
|
|
self->tx_buff.len = skb->len;
|
|
self->tx_buff.len = skb->len;
|
|
-
|
|
|
|
|
|
+
|
|
mtt = irda_get_mtt(skb);
|
|
mtt = irda_get_mtt(skb);
|
|
pr_debug("%s(%ld), mtt=%d\n", __func__ , jiffies, mtt);
|
|
pr_debug("%s(%ld), mtt=%d\n", __func__ , jiffies, mtt);
|
|
- if (mtt > 1000)
|
|
|
|
- mdelay(mtt/1000);
|
|
|
|
- else if (mtt)
|
|
|
|
- udelay(mtt);
|
|
|
|
|
|
+ if (mtt > 1000)
|
|
|
|
+ mdelay(mtt/1000);
|
|
|
|
+ else if (mtt)
|
|
|
|
+ udelay(mtt);
|
|
|
|
|
|
- /* Enable DMA interrupt */
|
|
|
|
- switch_bank(iobase, SET0);
|
|
|
|
- outb(ICR_EDMAI, iobase+ICR);
|
|
|
|
- w83977af_dma_write(self, iobase);
|
|
|
|
|
|
+ /* Enable DMA interrupt */
|
|
|
|
+ switch_bank(iobase, SET0);
|
|
|
|
+ outb(ICR_EDMAI, iobase+ICR);
|
|
|
|
+ w83977af_dma_write(self, iobase);
|
|
} else {
|
|
} else {
|
|
self->tx_buff.data = self->tx_buff.head;
|
|
self->tx_buff.data = self->tx_buff.head;
|
|
- self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
|
|
|
|
|
|
+ self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
|
|
self->tx_buff.truesize);
|
|
self->tx_buff.truesize);
|
|
-
|
|
|
|
|
|
+
|
|
/* Add interrupt on tx low level (will fire immediately) */
|
|
/* Add interrupt on tx low level (will fire immediately) */
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
outb(ICR_ETXTHI, iobase+ICR);
|
|
outb(ICR_ETXTHI, iobase+ICR);
|
|
@@ -562,15 +562,15 @@ static void w83977af_dma_write(struct w83977af_ir *self, int iobase)
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
|
|
outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
|
|
|
|
|
|
- /* Choose transmit DMA channel */
|
|
|
|
|
|
+ /* Choose transmit DMA channel */
|
|
switch_bank(iobase, SET2);
|
|
switch_bank(iobase, SET2);
|
|
outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1);
|
|
outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1);
|
|
irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
|
|
irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
|
|
- DMA_MODE_WRITE);
|
|
|
|
|
|
+ DMA_MODE_WRITE);
|
|
self->io.direction = IO_XMIT;
|
|
self->io.direction = IO_XMIT;
|
|
-
|
|
|
|
|
|
+
|
|
/* Enable DMA */
|
|
/* Enable DMA */
|
|
- switch_bank(iobase, SET0);
|
|
|
|
|
|
+ switch_bank(iobase, SET0);
|
|
outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR);
|
|
outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR);
|
|
|
|
|
|
/* Restore set register */
|
|
/* Restore set register */
|
|
@@ -580,14 +580,14 @@ static void w83977af_dma_write(struct w83977af_ir *self, int iobase)
|
|
/*
|
|
/*
|
|
* Function w83977af_pio_write (iobase, buf, len, fifo_size)
|
|
* Function w83977af_pio_write (iobase, buf, len, fifo_size)
|
|
*
|
|
*
|
|
- *
|
|
|
|
|
|
+ *
|
|
*
|
|
*
|
|
*/
|
|
*/
|
|
static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
|
|
static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
|
|
{
|
|
{
|
|
int actual = 0;
|
|
int actual = 0;
|
|
__u8 set;
|
|
__u8 set;
|
|
-
|
|
|
|
|
|
+
|
|
/* Save current bank */
|
|
/* Save current bank */
|
|
set = inb(iobase+SSR);
|
|
set = inb(iobase+SSR);
|
|
|
|
|
|
@@ -605,7 +605,7 @@ static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
|
|
/* Transmit next byte */
|
|
/* Transmit next byte */
|
|
outb(buf[actual++], iobase+TBR);
|
|
outb(buf[actual++], iobase+TBR);
|
|
}
|
|
}
|
|
-
|
|
|
|
|
|
+
|
|
pr_debug("%s(), fifo_size %d ; %d sent of %d\n",
|
|
pr_debug("%s(), fifo_size %d ; %d sent of %d\n",
|
|
__func__ , fifo_size, actual, len);
|
|
__func__ , fifo_size, actual, len);
|
|
|
|
|
|
@@ -620,7 +620,7 @@ static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
|
|
*
|
|
*
|
|
* The transfer of a frame in finished. So do the necessary things
|
|
* The transfer of a frame in finished. So do the necessary things
|
|
*
|
|
*
|
|
- *
|
|
|
|
|
|
+ *
|
|
*/
|
|
*/
|
|
static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
|
|
static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
|
|
{
|
|
{
|
|
@@ -639,11 +639,11 @@ static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
|
|
/* Disable DMA */
|
|
/* Disable DMA */
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
|
|
outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
|
|
-
|
|
|
|
|
|
+
|
|
/* Check for underrun! */
|
|
/* Check for underrun! */
|
|
if (inb(iobase+AUDR) & AUDR_UNDR) {
|
|
if (inb(iobase+AUDR) & AUDR_UNDR) {
|
|
pr_debug("%s(), Transmit underrun!\n", __func__);
|
|
pr_debug("%s(), Transmit underrun!\n", __func__);
|
|
-
|
|
|
|
|
|
+
|
|
self->netdev->stats.tx_errors++;
|
|
self->netdev->stats.tx_errors++;
|
|
self->netdev->stats.tx_fifo_errors++;
|
|
self->netdev->stats.tx_fifo_errors++;
|
|
|
|
|
|
@@ -652,7 +652,7 @@ static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
|
|
} else
|
|
} else
|
|
self->netdev->stats.tx_packets++;
|
|
self->netdev->stats.tx_packets++;
|
|
|
|
|
|
-
|
|
|
|
|
|
+
|
|
if (self->new_speed) {
|
|
if (self->new_speed) {
|
|
w83977af_change_speed(self, self->new_speed);
|
|
w83977af_change_speed(self, self->new_speed);
|
|
self->new_speed = 0;
|
|
self->new_speed = 0;
|
|
@@ -661,7 +661,7 @@ static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
|
|
/* Unlock tx_buff and request another frame */
|
|
/* Unlock tx_buff and request another frame */
|
|
/* Tell the network layer, that we want more frames */
|
|
/* Tell the network layer, that we want more frames */
|
|
netif_wake_queue(self->netdev);
|
|
netif_wake_queue(self->netdev);
|
|
-
|
|
|
|
|
|
+
|
|
/* Restore set */
|
|
/* Restore set */
|
|
outb(set, iobase+SSR);
|
|
outb(set, iobase+SSR);
|
|
}
|
|
}
|
|
@@ -714,15 +714,15 @@ static int w83977af_dma_receive(struct w83977af_ir *self)
|
|
irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
|
|
irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
|
|
DMA_MODE_READ);
|
|
DMA_MODE_READ);
|
|
#endif
|
|
#endif
|
|
- /*
|
|
|
|
- * Reset Rx FIFO. This will also flush the ST_FIFO, it's very
|
|
|
|
|
|
+ /*
|
|
|
|
+ * Reset Rx FIFO. This will also flush the ST_FIFO, it's very
|
|
* important that we don't reset the Tx FIFO since it might not
|
|
* important that we don't reset the Tx FIFO since it might not
|
|
* be finished transmitting yet
|
|
* be finished transmitting yet
|
|
*/
|
|
*/
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR);
|
|
outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR);
|
|
self->st_fifo.len = self->st_fifo.tail = self->st_fifo.head = 0;
|
|
self->st_fifo.len = self->st_fifo.tail = self->st_fifo.head = 0;
|
|
-
|
|
|
|
|
|
+
|
|
/* Enable DMA */
|
|
/* Enable DMA */
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
#ifdef CONFIG_ARCH_NETWINDER
|
|
#ifdef CONFIG_ARCH_NETWINDER
|
|
@@ -730,7 +730,7 @@ static int w83977af_dma_receive(struct w83977af_ir *self)
|
|
outb(hcr | HCR_EN_DMA, iobase+HCR);
|
|
outb(hcr | HCR_EN_DMA, iobase+HCR);
|
|
enable_dma(self->io.dma);
|
|
enable_dma(self->io.dma);
|
|
spin_unlock_irqrestore(&self->lock, flags);
|
|
spin_unlock_irqrestore(&self->lock, flags);
|
|
-#else
|
|
|
|
|
|
+#else
|
|
outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR);
|
|
outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR);
|
|
#endif
|
|
#endif
|
|
/* Restore set */
|
|
/* Restore set */
|
|
@@ -762,21 +762,21 @@ static int w83977af_dma_receive_complete(struct w83977af_ir *self)
|
|
|
|
|
|
/* Save current set */
|
|
/* Save current set */
|
|
set = inb(iobase+SSR);
|
|
set = inb(iobase+SSR);
|
|
-
|
|
|
|
|
|
+
|
|
iobase = self->io.fir_base;
|
|
iobase = self->io.fir_base;
|
|
|
|
|
|
/* Read status FIFO */
|
|
/* Read status FIFO */
|
|
switch_bank(iobase, SET5);
|
|
switch_bank(iobase, SET5);
|
|
while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) {
|
|
while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) {
|
|
st_fifo->entries[st_fifo->tail].status = status;
|
|
st_fifo->entries[st_fifo->tail].status = status;
|
|
-
|
|
|
|
|
|
+
|
|
st_fifo->entries[st_fifo->tail].len = inb(iobase+RFLFL);
|
|
st_fifo->entries[st_fifo->tail].len = inb(iobase+RFLFL);
|
|
st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8;
|
|
st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8;
|
|
-
|
|
|
|
|
|
+
|
|
st_fifo->tail++;
|
|
st_fifo->tail++;
|
|
st_fifo->len++;
|
|
st_fifo->len++;
|
|
}
|
|
}
|
|
-
|
|
|
|
|
|
+
|
|
while (st_fifo->len) {
|
|
while (st_fifo->len) {
|
|
/* Get first entry */
|
|
/* Get first entry */
|
|
status = st_fifo->entries[st_fifo->head].status;
|
|
status = st_fifo->entries[st_fifo->head].status;
|
|
@@ -792,32 +792,32 @@ static int w83977af_dma_receive_complete(struct w83977af_ir *self)
|
|
} else {
|
|
} else {
|
|
/* Skip frame */
|
|
/* Skip frame */
|
|
self->netdev->stats.rx_errors++;
|
|
self->netdev->stats.rx_errors++;
|
|
-
|
|
|
|
|
|
+
|
|
self->rx_buff.data += len;
|
|
self->rx_buff.data += len;
|
|
-
|
|
|
|
|
|
+
|
|
if (status & FS_FO_MX_LEX)
|
|
if (status & FS_FO_MX_LEX)
|
|
self->netdev->stats.rx_length_errors++;
|
|
self->netdev->stats.rx_length_errors++;
|
|
-
|
|
|
|
- if (status & FS_FO_PHY_ERR)
|
|
|
|
|
|
+
|
|
|
|
+ if (status & FS_FO_PHY_ERR)
|
|
self->netdev->stats.rx_frame_errors++;
|
|
self->netdev->stats.rx_frame_errors++;
|
|
-
|
|
|
|
- if (status & FS_FO_CRC_ERR)
|
|
|
|
|
|
+
|
|
|
|
+ if (status & FS_FO_CRC_ERR)
|
|
self->netdev->stats.rx_crc_errors++;
|
|
self->netdev->stats.rx_crc_errors++;
|
|
}
|
|
}
|
|
/* The errors below can be reported in both cases */
|
|
/* The errors below can be reported in both cases */
|
|
if (status & FS_FO_RX_OV)
|
|
if (status & FS_FO_RX_OV)
|
|
self->netdev->stats.rx_fifo_errors++;
|
|
self->netdev->stats.rx_fifo_errors++;
|
|
-
|
|
|
|
|
|
+
|
|
if (status & FS_FO_FSF_OV)
|
|
if (status & FS_FO_FSF_OV)
|
|
self->netdev->stats.rx_fifo_errors++;
|
|
self->netdev->stats.rx_fifo_errors++;
|
|
-
|
|
|
|
|
|
+
|
|
} else {
|
|
} else {
|
|
/* Check if we have transferred all data to memory */
|
|
/* Check if we have transferred all data to memory */
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
if (inb(iobase+USR) & USR_RDR) {
|
|
if (inb(iobase+USR) & USR_RDR) {
|
|
udelay(80); /* Should be enough!? */
|
|
udelay(80); /* Should be enough!? */
|
|
}
|
|
}
|
|
-
|
|
|
|
|
|
+
|
|
skb = dev_alloc_skb(len+1);
|
|
skb = dev_alloc_skb(len+1);
|
|
if (skb == NULL) {
|
|
if (skb == NULL) {
|
|
printk(KERN_INFO
|
|
printk(KERN_INFO
|
|
@@ -827,10 +827,10 @@ static int w83977af_dma_receive_complete(struct w83977af_ir *self)
|
|
|
|
|
|
return FALSE;
|
|
return FALSE;
|
|
}
|
|
}
|
|
-
|
|
|
|
|
|
+
|
|
/* Align to 20 bytes */
|
|
/* Align to 20 bytes */
|
|
- skb_reserve(skb, 1);
|
|
|
|
-
|
|
|
|
|
|
+ skb_reserve(skb, 1);
|
|
|
|
+
|
|
/* Copy frame without CRC */
|
|
/* Copy frame without CRC */
|
|
if (self->io.speed < 4000000) {
|
|
if (self->io.speed < 4000000) {
|
|
skb_put(skb, len-2);
|
|
skb_put(skb, len-2);
|
|
@@ -847,7 +847,7 @@ static int w83977af_dma_receive_complete(struct w83977af_ir *self)
|
|
/* Move to next frame */
|
|
/* Move to next frame */
|
|
self->rx_buff.data += len;
|
|
self->rx_buff.data += len;
|
|
self->netdev->stats.rx_packets++;
|
|
self->netdev->stats.rx_packets++;
|
|
-
|
|
|
|
|
|
+
|
|
skb->dev = self->netdev;
|
|
skb->dev = self->netdev;
|
|
skb_reset_mac_header(skb);
|
|
skb_reset_mac_header(skb);
|
|
skb->protocol = htons(ETH_P_IRDA);
|
|
skb->protocol = htons(ETH_P_IRDA);
|
|
@@ -866,21 +866,21 @@ static int w83977af_dma_receive_complete(struct w83977af_ir *self)
|
|
* Receive all data in receiver FIFO
|
|
* Receive all data in receiver FIFO
|
|
*
|
|
*
|
|
*/
|
|
*/
|
|
-static void w83977af_pio_receive(struct w83977af_ir *self)
|
|
|
|
|
|
+static void w83977af_pio_receive(struct w83977af_ir *self)
|
|
{
|
|
{
|
|
__u8 byte = 0x00;
|
|
__u8 byte = 0x00;
|
|
int iobase;
|
|
int iobase;
|
|
|
|
|
|
IRDA_ASSERT(self != NULL, return;);
|
|
IRDA_ASSERT(self != NULL, return;);
|
|
-
|
|
|
|
|
|
+
|
|
iobase = self->io.fir_base;
|
|
iobase = self->io.fir_base;
|
|
-
|
|
|
|
|
|
+
|
|
/* Receive all characters in Rx FIFO */
|
|
/* Receive all characters in Rx FIFO */
|
|
do {
|
|
do {
|
|
byte = inb(iobase+RBR);
|
|
byte = inb(iobase+RBR);
|
|
async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
|
|
async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
|
|
byte);
|
|
byte);
|
|
- } while (inb(iobase+USR) & USR_RDR); /* Data available */
|
|
|
|
|
|
+ } while (inb(iobase+USR) & USR_RDR); /* Data available */
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
/*
|
|
@@ -897,19 +897,19 @@ static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
|
|
int iobase;
|
|
int iobase;
|
|
|
|
|
|
pr_debug("%s(), isr=%#x\n", __func__ , isr);
|
|
pr_debug("%s(), isr=%#x\n", __func__ , isr);
|
|
-
|
|
|
|
|
|
+
|
|
iobase = self->io.fir_base;
|
|
iobase = self->io.fir_base;
|
|
/* Transmit FIFO low on data */
|
|
/* Transmit FIFO low on data */
|
|
if (isr & ISR_TXTH_I) {
|
|
if (isr & ISR_TXTH_I) {
|
|
/* Write data left in transmit buffer */
|
|
/* Write data left in transmit buffer */
|
|
- actual = w83977af_pio_write(self->io.fir_base,
|
|
|
|
- self->tx_buff.data,
|
|
|
|
- self->tx_buff.len,
|
|
|
|
|
|
+ actual = w83977af_pio_write(self->io.fir_base,
|
|
|
|
+ self->tx_buff.data,
|
|
|
|
+ self->tx_buff.len,
|
|
self->io.fifo_size);
|
|
self->io.fifo_size);
|
|
|
|
|
|
self->tx_buff.data += actual;
|
|
self->tx_buff.data += actual;
|
|
self->tx_buff.len -= actual;
|
|
self->tx_buff.len -= actual;
|
|
-
|
|
|
|
|
|
+
|
|
self->io.direction = IO_XMIT;
|
|
self->io.direction = IO_XMIT;
|
|
|
|
|
|
/* Check if finished */
|
|
/* Check if finished */
|
|
@@ -919,7 +919,7 @@ static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
|
|
set = inb(iobase+SSR);
|
|
set = inb(iobase+SSR);
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
outb(AUDR_SFEND, iobase+AUDR);
|
|
outb(AUDR_SFEND, iobase+AUDR);
|
|
- outb(set, iobase+SSR);
|
|
|
|
|
|
+ outb(set, iobase+SSR);
|
|
|
|
|
|
self->netdev->stats.tx_packets++;
|
|
self->netdev->stats.tx_packets++;
|
|
|
|
|
|
@@ -929,7 +929,7 @@ static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/* Check if transmission has completed */
|
|
/* Check if transmission has completed */
|
|
- if (isr & ISR_TXEMP_I) {
|
|
|
|
|
|
+ if (isr & ISR_TXEMP_I) {
|
|
/* Check if we need to change the speed? */
|
|
/* Check if we need to change the speed? */
|
|
if (self->new_speed) {
|
|
if (self->new_speed) {
|
|
pr_debug("%s(), Changing speed!\n", __func__);
|
|
pr_debug("%s(), Changing speed!\n", __func__);
|
|
@@ -966,11 +966,11 @@ static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
|
|
|
|
|
|
iobase = self->io.fir_base;
|
|
iobase = self->io.fir_base;
|
|
set = inb(iobase+SSR);
|
|
set = inb(iobase+SSR);
|
|
-
|
|
|
|
|
|
+
|
|
/* End of frame detected in FIFO */
|
|
/* End of frame detected in FIFO */
|
|
if (isr & (ISR_FEND_I|ISR_FSF_I)) {
|
|
if (isr & (ISR_FEND_I|ISR_FSF_I)) {
|
|
if (w83977af_dma_receive_complete(self)) {
|
|
if (w83977af_dma_receive_complete(self)) {
|
|
-
|
|
|
|
|
|
+
|
|
/* Wait for next status FIFO interrupt */
|
|
/* Wait for next status FIFO interrupt */
|
|
new_icr |= ICR_EFSFI;
|
|
new_icr |= ICR_EFSFI;
|
|
} else {
|
|
} else {
|
|
@@ -995,7 +995,7 @@ static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
|
|
|
|
|
|
/* Clear timer event */
|
|
/* Clear timer event */
|
|
/* switch_bank(iobase, SET0); */
|
|
/* switch_bank(iobase, SET0); */
|
|
-/* outb(ASCR_CTE, iobase+ASCR); */
|
|
|
|
|
|
+/* outb(ASCR_CTE, iobase+ASCR); */
|
|
|
|
|
|
/* Check if this is a TX timer interrupt */
|
|
/* Check if this is a TX timer interrupt */
|
|
if (self->io.direction == IO_XMIT) {
|
|
if (self->io.direction == IO_XMIT) {
|
|
@@ -1008,23 +1008,23 @@ static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
|
|
|
|
|
|
new_icr |= ICR_EFSFI;
|
|
new_icr |= ICR_EFSFI;
|
|
}
|
|
}
|
|
- }
|
|
|
|
|
|
+ }
|
|
/* Finished with DMA */
|
|
/* Finished with DMA */
|
|
if (isr & ISR_DMA_I) {
|
|
if (isr & ISR_DMA_I) {
|
|
w83977af_dma_xmit_complete(self);
|
|
w83977af_dma_xmit_complete(self);
|
|
|
|
|
|
/* Check if there are more frames to be transmitted */
|
|
/* Check if there are more frames to be transmitted */
|
|
/* if (irda_device_txqueue_empty(self)) { */
|
|
/* if (irda_device_txqueue_empty(self)) { */
|
|
-
|
|
|
|
- /* Prepare for receive
|
|
|
|
- *
|
|
|
|
|
|
+
|
|
|
|
+ /* Prepare for receive
|
|
|
|
+ *
|
|
* ** Netwinder Tx DMA likes that we do this anyway **
|
|
* ** Netwinder Tx DMA likes that we do this anyway **
|
|
*/
|
|
*/
|
|
w83977af_dma_receive(self);
|
|
w83977af_dma_receive(self);
|
|
new_icr = ICR_EFSFI;
|
|
new_icr = ICR_EFSFI;
|
|
- /* } */
|
|
|
|
|
|
+ /* } */
|
|
}
|
|
}
|
|
-
|
|
|
|
|
|
+
|
|
/* Restore set */
|
|
/* Restore set */
|
|
outb(set, iobase+SSR);
|
|
outb(set, iobase+SSR);
|
|
|
|
|
|
@@ -1051,12 +1051,12 @@ static irqreturn_t w83977af_interrupt(int irq, void *dev_id)
|
|
/* Save current bank */
|
|
/* Save current bank */
|
|
set = inb(iobase+SSR);
|
|
set = inb(iobase+SSR);
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
-
|
|
|
|
- icr = inb(iobase+ICR);
|
|
|
|
- isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */
|
|
|
|
|
|
+
|
|
|
|
+ icr = inb(iobase+ICR);
|
|
|
|
+ isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */
|
|
|
|
|
|
outb(0, iobase+ICR); /* Disable interrupts */
|
|
outb(0, iobase+ICR); /* Disable interrupts */
|
|
-
|
|
|
|
|
|
+
|
|
if (isr) {
|
|
if (isr) {
|
|
/* Dispatch interrupt handler for the current speed */
|
|
/* Dispatch interrupt handler for the current speed */
|
|
if (self->io.speed > PIO_MAX_SPEED )
|
|
if (self->io.speed > PIO_MAX_SPEED )
|
|
@@ -1095,9 +1095,9 @@ static int w83977af_is_receiving(struct w83977af_ir *self)
|
|
status = TRUE;
|
|
status = TRUE;
|
|
}
|
|
}
|
|
outb(set, iobase+SSR);
|
|
outb(set, iobase+SSR);
|
|
- } else
|
|
|
|
|
|
+ } else
|
|
status = (self->rx_buff.state != OUTSIDE_FRAME);
|
|
status = (self->rx_buff.state != OUTSIDE_FRAME);
|
|
-
|
|
|
|
|
|
+
|
|
return status;
|
|
return status;
|
|
}
|
|
}
|
|
|
|
|
|
@@ -1113,16 +1113,16 @@ static int w83977af_net_open(struct net_device *dev)
|
|
int iobase;
|
|
int iobase;
|
|
char hwname[32];
|
|
char hwname[32];
|
|
__u8 set;
|
|
__u8 set;
|
|
-
|
|
|
|
-
|
|
|
|
|
|
+
|
|
|
|
+
|
|
IRDA_ASSERT(dev != NULL, return -1;);
|
|
IRDA_ASSERT(dev != NULL, return -1;);
|
|
self = netdev_priv(dev);
|
|
self = netdev_priv(dev);
|
|
-
|
|
|
|
|
|
+
|
|
IRDA_ASSERT(self != NULL, return 0;);
|
|
IRDA_ASSERT(self != NULL, return 0;);
|
|
-
|
|
|
|
|
|
+
|
|
iobase = self->io.fir_base;
|
|
iobase = self->io.fir_base;
|
|
|
|
|
|
- if (request_irq(self->io.irq, w83977af_interrupt, 0, dev->name,
|
|
|
|
|
|
+ if (request_irq(self->io.irq, w83977af_interrupt, 0, dev->name,
|
|
(void *) dev)) {
|
|
(void *) dev)) {
|
|
return -EAGAIN;
|
|
return -EAGAIN;
|
|
}
|
|
}
|
|
@@ -1134,30 +1134,30 @@ static int w83977af_net_open(struct net_device *dev)
|
|
free_irq(self->io.irq, dev);
|
|
free_irq(self->io.irq, dev);
|
|
return -EAGAIN;
|
|
return -EAGAIN;
|
|
}
|
|
}
|
|
-
|
|
|
|
|
|
+
|
|
/* Save current set */
|
|
/* Save current set */
|
|
set = inb(iobase+SSR);
|
|
set = inb(iobase+SSR);
|
|
|
|
|
|
- /* Enable some interrupts so we can receive frames again */
|
|
|
|
- switch_bank(iobase, SET0);
|
|
|
|
- if (self->io.speed > 115200) {
|
|
|
|
- outb(ICR_EFSFI, iobase+ICR);
|
|
|
|
- w83977af_dma_receive(self);
|
|
|
|
- } else
|
|
|
|
- outb(ICR_ERBRI, iobase+ICR);
|
|
|
|
|
|
+ /* Enable some interrupts so we can receive frames again */
|
|
|
|
+ switch_bank(iobase, SET0);
|
|
|
|
+ if (self->io.speed > 115200) {
|
|
|
|
+ outb(ICR_EFSFI, iobase+ICR);
|
|
|
|
+ w83977af_dma_receive(self);
|
|
|
|
+ } else
|
|
|
|
+ outb(ICR_ERBRI, iobase+ICR);
|
|
|
|
|
|
/* Restore bank register */
|
|
/* Restore bank register */
|
|
outb(set, iobase+SSR);
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|
outb(set, iobase+SSR);
|
|
|
|
|
|
/* Ready to play! */
|
|
/* Ready to play! */
|
|
netif_start_queue(dev);
|
|
netif_start_queue(dev);
|
|
-
|
|
|
|
|
|
+
|
|
/* Give self a hardware name */
|
|
/* Give self a hardware name */
|
|
sprintf(hwname, "w83977af @ 0x%03x", self->io.fir_base);
|
|
sprintf(hwname, "w83977af @ 0x%03x", self->io.fir_base);
|
|
|
|
|
|
- /*
|
|
|
|
|
|
+ /*
|
|
* Open new IrLAP layer instance, now that everything should be
|
|
* Open new IrLAP layer instance, now that everything should be
|
|
- * initialized properly
|
|
|
|
|
|
+ * initialized properly
|
|
*/
|
|
*/
|
|
self->irlap = irlap_open(dev, &self->qos, hwname);
|
|
self->irlap = irlap_open(dev, &self->qos, hwname);
|
|
|
|
|
|
@@ -1177,16 +1177,16 @@ static int w83977af_net_close(struct net_device *dev)
|
|
__u8 set;
|
|
__u8 set;
|
|
|
|
|
|
IRDA_ASSERT(dev != NULL, return -1;);
|
|
IRDA_ASSERT(dev != NULL, return -1;);
|
|
-
|
|
|
|
|
|
+
|
|
self = netdev_priv(dev);
|
|
self = netdev_priv(dev);
|
|
-
|
|
|
|
|
|
+
|
|
IRDA_ASSERT(self != NULL, return 0;);
|
|
IRDA_ASSERT(self != NULL, return 0;);
|
|
-
|
|
|
|
|
|
+
|
|
iobase = self->io.fir_base;
|
|
iobase = self->io.fir_base;
|
|
|
|
|
|
/* Stop device */
|
|
/* Stop device */
|
|
netif_stop_queue(dev);
|
|
netif_stop_queue(dev);
|
|
-
|
|
|
|
|
|
+
|
|
/* Stop and remove instance of IrLAP */
|
|
/* Stop and remove instance of IrLAP */
|
|
if (self->irlap)
|
|
if (self->irlap)
|
|
irlap_close(self->irlap);
|
|
irlap_close(self->irlap);
|
|
@@ -1196,10 +1196,10 @@ static int w83977af_net_close(struct net_device *dev)
|
|
|
|
|
|
/* Save current set */
|
|
/* Save current set */
|
|
set = inb(iobase+SSR);
|
|
set = inb(iobase+SSR);
|
|
-
|
|
|
|
|
|
+
|
|
/* Disable interrupts */
|
|
/* Disable interrupts */
|
|
switch_bank(iobase, SET0);
|
|
switch_bank(iobase, SET0);
|
|
- outb(0, iobase+ICR);
|
|
|
|
|
|
+ outb(0, iobase+ICR);
|
|
|
|
|
|
free_irq(self->io.irq, dev);
|
|
free_irq(self->io.irq, dev);
|
|
free_dma(self->io.dma);
|
|
free_dma(self->io.dma);
|
|
@@ -1230,7 +1230,7 @@ static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
|
|
IRDA_ASSERT(self != NULL, return -1;);
|
|
IRDA_ASSERT(self != NULL, return -1;);
|
|
|
|
|
|
pr_debug("%s(), %s, (cmd=0x%X)\n", __func__ , dev->name, cmd);
|
|
pr_debug("%s(), %s, (cmd=0x%X)\n", __func__ , dev->name, cmd);
|
|
-
|
|
|
|
|
|
+
|
|
spin_lock_irqsave(&self->lock, flags);
|
|
spin_lock_irqsave(&self->lock, flags);
|
|
|
|
|
|
switch (cmd) {
|
|
switch (cmd) {
|
|
@@ -1274,7 +1274,7 @@ MODULE_PARM_DESC(irq, "IRQ lines");
|
|
/*
|
|
/*
|
|
* Function init_module (void)
|
|
* Function init_module (void)
|
|
*
|
|
*
|
|
- *
|
|
|
|
|
|
+ *
|
|
*
|
|
*
|
|
*/
|
|
*/
|
|
module_init(w83977af_init);
|
|
module_init(w83977af_init);
|
|
@@ -1282,7 +1282,7 @@ module_init(w83977af_init);
|
|
/*
|
|
/*
|
|
* Function cleanup_module (void)
|
|
* Function cleanup_module (void)
|
|
*
|
|
*
|
|
- *
|
|
|
|
|
|
+ *
|
|
*
|
|
*
|
|
*/
|
|
*/
|
|
module_exit(w83977af_cleanup);
|
|
module_exit(w83977af_cleanup);
|