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@@ -32,6 +32,41 @@
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#include <asm/spram.h>
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#include <asm/uaccess.h>
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+/*
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+ * Get the FPU Implementation/Revision.
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+ */
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+static inline unsigned long cpu_get_fpu_id(void)
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+{
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+ unsigned long tmp, fpu_id;
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+
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+ tmp = read_c0_status();
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+ __enable_fpu(FPU_AS_IS);
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+ fpu_id = read_32bit_cp1_register(CP1_REVISION);
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+ write_c0_status(tmp);
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+ return fpu_id;
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+}
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+
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+/*
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+ * Check if the CPU has an external FPU.
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+ */
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+static inline int __cpu_has_fpu(void)
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+{
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+ return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
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+}
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+
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+static inline unsigned long cpu_get_msa_id(void)
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+{
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+ unsigned long status, msa_id;
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+
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+ status = read_c0_status();
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+ __enable_fpu(FPU_64BIT);
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+ enable_msa();
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+ msa_id = read_msa_ir();
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+ disable_msa();
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+ write_c0_status(status);
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+ return msa_id;
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+}
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+
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/*
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* Determine the FCSR mask for FPU hardware.
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*/
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@@ -82,13 +117,42 @@ static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
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/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
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static unsigned int mips_nofpu_msk31;
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+/*
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+ * Set options for FPU hardware.
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+ */
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+static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
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+{
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+ c->fpu_id = cpu_get_fpu_id();
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+ mips_nofpu_msk31 = c->fpu_msk31;
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+
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+ if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
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+ MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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+ MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
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+ if (c->fpu_id & MIPS_FPIR_3D)
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+ c->ases |= MIPS_ASE_MIPS3D;
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+ if (c->fpu_id & MIPS_FPIR_FREP)
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+ c->options |= MIPS_CPU_FRE;
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+ }
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+
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+ cpu_set_fpu_fcsr_mask(c);
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+}
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+
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+/*
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+ * Set options for the FPU emulator.
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+ */
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+static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
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+{
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+ c->options &= ~MIPS_CPU_FPU;
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+ c->fpu_msk31 = mips_nofpu_msk31;
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+
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+ cpu_set_nofpu_id(c);
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+}
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+
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static int mips_fpu_disabled;
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static int __init fpu_disable(char *s)
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{
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- boot_cpu_data.options &= ~MIPS_CPU_FPU;
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- boot_cpu_data.fpu_msk31 = mips_nofpu_msk31;
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- cpu_set_nofpu_id(&boot_cpu_data);
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+ cpu_set_nofpu_opts(&boot_cpu_data);
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mips_fpu_disabled = 1;
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return 1;
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@@ -231,41 +295,6 @@ static inline void set_elf_platform(int cpu, const char *plat)
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__elf_platform = plat;
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}
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-/*
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- * Get the FPU Implementation/Revision.
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- */
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-static inline unsigned long cpu_get_fpu_id(void)
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-{
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- unsigned long tmp, fpu_id;
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-
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- tmp = read_c0_status();
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- __enable_fpu(FPU_AS_IS);
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- fpu_id = read_32bit_cp1_register(CP1_REVISION);
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- write_c0_status(tmp);
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- return fpu_id;
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-}
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-
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-/*
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- * Check if the CPU has an external FPU.
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- */
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-static inline int __cpu_has_fpu(void)
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-{
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- return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
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-}
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-
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-static inline unsigned long cpu_get_msa_id(void)
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-{
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- unsigned long status, msa_id;
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-
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- status = read_c0_status();
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- __enable_fpu(FPU_64BIT);
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- enable_msa();
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- msa_id = read_msa_ir();
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- disable_msa();
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- write_c0_status(status);
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- return msa_id;
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-}
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-
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static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
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{
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#ifdef __NEED_VMBITS_PROBE
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@@ -1441,22 +1470,10 @@ void cpu_probe(void)
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~(1 << MIPS_PWCTL_PWEN_SHIFT));
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}
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- if (c->options & MIPS_CPU_FPU) {
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- c->fpu_id = cpu_get_fpu_id();
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- mips_nofpu_msk31 = c->fpu_msk31;
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-
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- if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
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- MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
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- MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
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- if (c->fpu_id & MIPS_FPIR_3D)
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- c->ases |= MIPS_ASE_MIPS3D;
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- if (c->fpu_id & MIPS_FPIR_FREP)
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- c->options |= MIPS_CPU_FRE;
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- }
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-
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- cpu_set_fpu_fcsr_mask(c);
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- } else
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- cpu_set_nofpu_id(c);
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+ if (c->options & MIPS_CPU_FPU)
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+ cpu_set_fpu_opts(c);
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+ else
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+ cpu_set_nofpu_opts(c);
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if (cpu_has_mips_r2_r6) {
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c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
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