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@@ -681,12 +681,17 @@ static const struct iommu_ops *iort_iommu_xlate(struct device *dev,
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}
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/**
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- * iort_set_dma_mask - Set-up dma mask for a device.
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+ * iort_dma_setup() - Set-up device DMA parameters.
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*
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* @dev: device to configure
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+ * @dma_addr: device DMA address result pointer
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+ * @size: DMA range size result pointer
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*/
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-void iort_set_dma_mask(struct device *dev)
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+void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *dma_size)
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{
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+ u64 mask, dmaaddr = 0, size = 0, offset = 0;
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+ int ret, msb;
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+
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/*
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* Set default coherent_dma_mask to 32 bit. Drivers are expected to
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* setup the correct supported mask.
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@@ -700,6 +705,34 @@ void iort_set_dma_mask(struct device *dev)
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*/
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if (!dev->dma_mask)
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dev->dma_mask = &dev->coherent_dma_mask;
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+
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+ size = max(dev->coherent_dma_mask, dev->coherent_dma_mask + 1);
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+
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+ if (dev_is_pci(dev)) {
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+ ret = acpi_dma_get_range(dev, &dmaaddr, &offset, &size);
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+ if (!ret) {
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+ msb = fls64(dmaaddr + size - 1);
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+ /*
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+ * Round-up to the power-of-two mask or set
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+ * the mask to the whole 64-bit address space
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+ * in case the DMA region covers the full
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+ * memory window.
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+ */
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+ mask = msb == 64 ? U64_MAX : (1ULL << msb) - 1;
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+ /*
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+ * Limit coherent and dma mask based on size
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+ * retrieved from firmware.
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+ */
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+ dev->coherent_dma_mask = mask;
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+ *dev->dma_mask = mask;
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+ }
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+ }
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+
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+ *dma_addr = dmaaddr;
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+ *dma_size = size;
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+
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+ dev->dma_pfn_offset = PFN_DOWN(offset);
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+ dev_dbg(dev, "dma_pfn_offset(%#08llx)\n", offset);
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}
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/**
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