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@@ -0,0 +1,109 @@
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+#ifndef __ASM_X86_REFCOUNT_H
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+#define __ASM_X86_REFCOUNT_H
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+/*
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+ * x86-specific implementation of refcount_t. Based on PAX_REFCOUNT from
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+ * PaX/grsecurity.
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+ */
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+#include <linux/refcount.h>
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+
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+/*
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+ * This is the first portion of the refcount error handling, which lives in
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+ * .text.unlikely, and is jumped to from the CPU flag check (in the
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+ * following macros). This saves the refcount value location into CX for
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+ * the exception handler to use (in mm/extable.c), and then triggers the
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+ * central refcount exception. The fixup address for the exception points
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+ * back to the regular execution flow in .text.
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+ */
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+#define _REFCOUNT_EXCEPTION \
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+ ".pushsection .text.unlikely\n" \
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+ "111:\tlea %[counter], %%" _ASM_CX "\n" \
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+ "112:\t" ASM_UD0 "\n" \
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+ ASM_UNREACHABLE \
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+ ".popsection\n" \
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+ "113:\n" \
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+ _ASM_EXTABLE_REFCOUNT(112b, 113b)
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+
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+/* Trigger refcount exception if refcount result is negative. */
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+#define REFCOUNT_CHECK_LT_ZERO \
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+ "js 111f\n\t" \
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+ _REFCOUNT_EXCEPTION
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+
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+/* Trigger refcount exception if refcount result is zero or negative. */
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+#define REFCOUNT_CHECK_LE_ZERO \
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+ "jz 111f\n\t" \
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+ REFCOUNT_CHECK_LT_ZERO
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+
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+/* Trigger refcount exception unconditionally. */
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+#define REFCOUNT_ERROR \
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+ "jmp 111f\n\t" \
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+ _REFCOUNT_EXCEPTION
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+
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+static __always_inline void refcount_add(unsigned int i, refcount_t *r)
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+{
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+ asm volatile(LOCK_PREFIX "addl %1,%0\n\t"
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+ REFCOUNT_CHECK_LT_ZERO
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+ : [counter] "+m" (r->refs.counter)
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+ : "ir" (i)
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+ : "cc", "cx");
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+}
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+
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+static __always_inline void refcount_inc(refcount_t *r)
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+{
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+ asm volatile(LOCK_PREFIX "incl %0\n\t"
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+ REFCOUNT_CHECK_LT_ZERO
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+ : [counter] "+m" (r->refs.counter)
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+ : : "cc", "cx");
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+}
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+
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+static __always_inline void refcount_dec(refcount_t *r)
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+{
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+ asm volatile(LOCK_PREFIX "decl %0\n\t"
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+ REFCOUNT_CHECK_LE_ZERO
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+ : [counter] "+m" (r->refs.counter)
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+ : : "cc", "cx");
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+}
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+
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+static __always_inline __must_check
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+bool refcount_sub_and_test(unsigned int i, refcount_t *r)
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+{
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+ GEN_BINARY_SUFFIXED_RMWcc(LOCK_PREFIX "subl", REFCOUNT_CHECK_LT_ZERO,
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+ r->refs.counter, "er", i, "%0", e);
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+}
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+
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+static __always_inline __must_check bool refcount_dec_and_test(refcount_t *r)
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+{
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+ GEN_UNARY_SUFFIXED_RMWcc(LOCK_PREFIX "decl", REFCOUNT_CHECK_LT_ZERO,
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+ r->refs.counter, "%0", e);
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+}
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+
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+static __always_inline __must_check
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+bool refcount_add_not_zero(unsigned int i, refcount_t *r)
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+{
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+ int c, result;
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+
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+ c = atomic_read(&(r->refs));
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+ do {
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+ if (unlikely(c == 0))
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+ return false;
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+
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+ result = c + i;
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+
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+ /* Did we try to increment from/to an undesirable state? */
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+ if (unlikely(c < 0 || c == INT_MAX || result < c)) {
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+ asm volatile(REFCOUNT_ERROR
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+ : : [counter] "m" (r->refs.counter)
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+ : "cc", "cx");
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+ break;
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+ }
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+
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+ } while (!atomic_try_cmpxchg(&(r->refs), &c, result));
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+
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+ return c != 0;
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+}
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+
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+static __always_inline __must_check bool refcount_inc_not_zero(refcount_t *r)
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+{
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+ return refcount_add_not_zero(1, r);
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+}
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+
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+#endif
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