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@@ -1060,16 +1060,7 @@ static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
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static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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- struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
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- struct bcm2835_cprman *cprman = divider->cprman;
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- const struct bcm2835_pll_divider_data *data = divider->data;
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- u32 div = cprman_read(cprman, data->a2w_reg);
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-
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- div &= (1 << A2W_PLL_DIV_BITS) - 1;
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- if (div == 0)
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- div = 256;
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-
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- return parent_rate / div;
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+ return clk_divider_ops.recalc_rate(hw, parent_rate);
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}
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static void bcm2835_pll_divider_off(struct clk_hw *hw)
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@@ -1430,7 +1421,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
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divider->div.reg = cprman->regs + data->a2w_reg;
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divider->div.shift = A2W_PLL_DIV_SHIFT;
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divider->div.width = A2W_PLL_DIV_BITS;
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- divider->div.flags = 0;
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+ divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
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divider->div.lock = &cprman->regs_lock;
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divider->div.hw.init = &init;
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divider->div.table = NULL;
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