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@@ -54,12 +54,19 @@ static int cpg_div6_clock_enable(struct clk_hw *hw)
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static void cpg_div6_clock_disable(struct clk_hw *hw)
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{
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struct div6_clock *clock = to_div6_clock(hw);
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+ u32 val;
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- /* DIV6 clocks require the divisor field to be non-zero when stopping
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- * the clock.
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+ val = clk_readl(clock->reg);
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+ val |= CPG_DIV6_CKSTP;
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+ /*
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+ * DIV6 clocks require the divisor field to be non-zero when stopping
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+ * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be
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+ * re-enabled later if the divisor field is changed when stopping the
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+ * clock
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*/
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- clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK,
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- clock->reg);
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+ if (!(val & CPG_DIV6_DIV_MASK))
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+ val |= CPG_DIV6_DIV_MASK;
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+ clk_writel(val, clock->reg);
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}
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static int cpg_div6_clock_is_enabled(struct clk_hw *hw)
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