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drm/radeon: use hw cts/n values for deep color

I'm not really sure how these should be calculated
for deep color.  The hw generated values seem to work.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher 11 years ago
parent
commit
79766915d9
1 changed files with 15 additions and 3 deletions
  1. 15 3
      drivers/gpu/drm/radeon/evergreen_hdmi.c

+ 15 - 3
drivers/gpu/drm/radeon/evergreen_hdmi.c

@@ -293,10 +293,12 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_device *rdev = dev->dev_private;
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
+	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 	struct hdmi_avi_infoframe frame;
 	struct hdmi_avi_infoframe frame;
 	uint32_t offset;
 	uint32_t offset;
 	ssize_t err;
 	ssize_t err;
+	int bpc = 8;
 
 
 	if (!dig || !dig->afmt)
 	if (!dig || !dig->afmt)
 		return;
 		return;
@@ -306,6 +308,12 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 		return;
 		return;
 	offset = dig->afmt->offset;
 	offset = dig->afmt->offset;
 
 
+	/* hdmi deep color mode general control packets setup, if bpc > 8 */
+	if (encoder->crtc) {
+		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
+		bpc = radeon_crtc->bpc;
+	}
+
 	/* disable audio prior to setting up hw */
 	/* disable audio prior to setting up hw */
 	if (ASIC_IS_DCE6(rdev)) {
 	if (ASIC_IS_DCE6(rdev)) {
 		dig->afmt->pin = dce6_audio_get_pin(rdev);
 		dig->afmt->pin = dce6_audio_get_pin(rdev);
@@ -348,9 +356,13 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
 
 
 	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
 	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
 
 
-	WREG32(HDMI_ACR_PACKET_CONTROL + offset,
-	       HDMI_ACR_SOURCE | /* select SW CTS value */
-	       HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
+	if (bpc > 8)
+		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
+		       HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
+	else
+		WREG32(HDMI_ACR_PACKET_CONTROL + offset,
+		       HDMI_ACR_SOURCE | /* select SW CTS value */
+		       HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
 
 
 	evergreen_hdmi_update_ACR(encoder, mode->clock);
 	evergreen_hdmi_update_ACR(encoder, mode->clock);