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@@ -2854,19 +2854,38 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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return false;
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hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
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+ hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
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+
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hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
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hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
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hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
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+ hw_state->pll0 &= PORT_PLL_M2_MASK;
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+
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hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
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+ hw_state->pll1 &= PORT_PLL_N_MASK;
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+
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hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
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+ hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
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+
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hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
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+ hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
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+
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hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
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+ hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
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+ PORT_PLL_INT_COEFF_MASK |
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+ PORT_PLL_GAIN_CTL_MASK;
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+
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hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
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+ hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
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+
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hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
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hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
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hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
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+ hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
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+ PORT_PLL_DCO_AMP_MASK;
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+
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/*
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* While we write to the group register to program all lanes at once we
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* can read only lane registers. We configure all lanes the same way, so
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@@ -2877,6 +2896,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
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hw_state->pcsdw12,
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I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
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+ hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
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return true;
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}
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