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@@ -209,6 +209,16 @@ static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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+static const u32 vga_control_regs[6] =
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+{
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+ AVIVO_D1VGA_CONTROL,
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+ AVIVO_D2VGA_CONTROL,
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+ EVERGREEN_D3VGA_CONTROL,
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+ EVERGREEN_D4VGA_CONTROL,
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+ EVERGREEN_D5VGA_CONTROL,
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+ EVERGREEN_D6VGA_CONTROL,
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+};
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+
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static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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@@ -216,13 +226,23 @@ static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
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struct radeon_device *rdev = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
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BLANK_CRTC_PS_ALLOCATION args;
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+ u32 vga_control = 0;
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memset(&args, 0, sizeof(args));
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+ if (ASIC_IS_DCE8(rdev)) {
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+ vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
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+ WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
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+ }
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+
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucBlanking = state;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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+
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+ if (ASIC_IS_DCE8(rdev)) {
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+ WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
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+ }
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}
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static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
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