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@@ -23,7 +23,14 @@
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#define VOP_REG(off, _mask, s) \
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{.offset = off, \
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.mask = _mask, \
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- .shift = s,}
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+ .shift = s, \
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+ .write_mask = false,}
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+
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+#define VOP_REG_MASK(off, _mask, s) \
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+ {.offset = off, \
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+ .mask = _mask, \
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+ .shift = s, \
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+ .write_mask = true,}
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static const uint32_t formats_win_full[] = {
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DRM_FORMAT_XRGB8888,
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@@ -50,6 +57,89 @@ static const uint32_t formats_win_lite[] = {
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DRM_FORMAT_BGR565,
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};
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+static const struct vop_scl_regs rk3036_win_scl = {
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+ .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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+ .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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+ .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
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+ .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
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+};
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+
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+static const struct vop_win_phy rk3036_win0_data = {
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+ .scl = &rk3036_win_scl,
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+ .data_formats = formats_win_full,
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+ .nformats = ARRAY_SIZE(formats_win_full),
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+ .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
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+ .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
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+ .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
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+ .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
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+ .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
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+ .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
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+ .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
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+ .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
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+ .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
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+ .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
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+};
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+
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+static const struct vop_win_phy rk3036_win1_data = {
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+ .data_formats = formats_win_lite,
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+ .nformats = ARRAY_SIZE(formats_win_lite),
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+ .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
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+ .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
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+ .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
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+ .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
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+ .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
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+ .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
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+ .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
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+ .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
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+};
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+
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+static const struct vop_win_data rk3036_vop_win_data[] = {
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+ { .base = 0x00, .phy = &rk3036_win0_data,
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+ .type = DRM_PLANE_TYPE_PRIMARY },
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+ { .base = 0x00, .phy = &rk3036_win1_data,
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+ .type = DRM_PLANE_TYPE_CURSOR },
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+};
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+
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+static const int rk3036_vop_intrs[] = {
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+ DSP_HOLD_VALID_INTR,
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+ FS_INTR,
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+ LINE_FLAG_INTR,
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+ BUS_ERROR_INTR,
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+};
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+
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+static const struct vop_intr rk3036_intr = {
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+ .intrs = rk3036_vop_intrs,
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+ .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
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+ .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
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+ .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
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+ .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
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+};
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+
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+static const struct vop_ctrl rk3036_ctrl_data = {
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+ .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
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+ .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
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+ .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
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+ .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
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+ .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
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+ .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
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+ .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
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+ .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
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+ .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
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+};
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+
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+static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
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+ {RK3036_DSP_CTRL1, 0x00000000},
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+};
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+
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+static const struct vop_data rk3036_vop = {
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+ .init_table = rk3036_vop_init_reg_table,
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+ .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
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+ .ctrl = &rk3036_ctrl_data,
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+ .intr = &rk3036_intr,
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+ .win = rk3036_vop_win_data,
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+ .win_size = ARRAY_SIZE(rk3036_vop_win_data),
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+};
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+
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static const struct vop_scl_extension rk3288_win_full_scl_ext = {
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.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
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.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
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@@ -133,6 +223,7 @@ static const struct vop_ctrl rk3288_ctrl_data = {
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.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
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.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
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.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
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+ .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
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.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
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};
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@@ -190,93 +281,104 @@ static const struct vop_data rk3288_vop = {
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.win_size = ARRAY_SIZE(rk3288_vop_win_data),
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};
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-static const struct vop_scl_regs rk3036_win_scl = {
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- .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
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- .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
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- .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
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- .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
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-};
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-
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-static const struct vop_win_phy rk3036_win0_data = {
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- .scl = &rk3036_win_scl,
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- .data_formats = formats_win_full,
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- .nformats = ARRAY_SIZE(formats_win_full),
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- .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
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- .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
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- .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
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- .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
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- .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
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- .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
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- .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
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- .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
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- .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
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- .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
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+static const struct vop_ctrl rk3399_ctrl_data = {
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+ .standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
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+ .gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
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+ .rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
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+ .hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
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+ .edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
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+ .mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
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+ .dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
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+ .dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
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+ .data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
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+ .out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
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+ .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
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+ .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
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+ .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
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+ .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
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+ .htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
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+ .hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
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+ .vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
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+ .vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
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+ .hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
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+ .vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
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+ .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0),
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+ .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16),
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+ .cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
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};
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-static const struct vop_win_phy rk3036_win1_data = {
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- .data_formats = formats_win_lite,
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- .nformats = ARRAY_SIZE(formats_win_lite),
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- .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
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- .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
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- .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
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- .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
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- .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
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- .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
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- .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
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- .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
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-};
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-
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-static const struct vop_win_data rk3036_vop_win_data[] = {
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- { .base = 0x00, .phy = &rk3036_win0_data,
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- .type = DRM_PLANE_TYPE_PRIMARY },
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- { .base = 0x00, .phy = &rk3036_win1_data,
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- .type = DRM_PLANE_TYPE_CURSOR },
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-};
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-
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-static const int rk3036_vop_intrs[] = {
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- DSP_HOLD_VALID_INTR,
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+static const int rk3399_vop_intrs[] = {
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FS_INTR,
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+ 0, 0,
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LINE_FLAG_INTR,
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+ 0,
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BUS_ERROR_INTR,
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+ 0, 0, 0, 0, 0, 0, 0,
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+ DSP_HOLD_VALID_INTR,
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};
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-static const struct vop_intr rk3036_intr = {
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- .intrs = rk3036_vop_intrs,
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- .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
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- .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
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- .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
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- .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
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+static const struct vop_intr rk3399_vop_intr = {
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+ .intrs = rk3399_vop_intrs,
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+ .nintrs = ARRAY_SIZE(rk3399_vop_intrs),
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+ .status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
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+ .enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
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+ .clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
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};
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-static const struct vop_ctrl rk3036_ctrl_data = {
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- .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
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- .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
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- .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
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- .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
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- .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
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- .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
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- .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
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- .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
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+static const struct vop_reg_data rk3399_init_reg_table[] = {
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+ {RK3399_SYS_CTRL, 0x2000f800},
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+ {RK3399_DSP_CTRL0, 0x00000000},
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+ {RK3399_WIN0_CTRL0, 0x00000080},
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+ {RK3399_WIN1_CTRL0, 0x00000080},
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+ /* TODO: Win2/3 support multiple area function, but we haven't found
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+ * a suitable way to use it yet, so let's just use them as other windows
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+ * with only area 0 enabled.
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+ */
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+ {RK3399_WIN2_CTRL0, 0x00000010},
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+ {RK3399_WIN3_CTRL0, 0x00000010},
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};
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-static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
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- {RK3036_DSP_CTRL1, 0x00000000},
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+static const struct vop_data rk3399_vop_big = {
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+ .init_table = rk3399_init_reg_table,
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+ .table_size = ARRAY_SIZE(rk3399_init_reg_table),
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+ .intr = &rk3399_vop_intr,
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+ .ctrl = &rk3399_ctrl_data,
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+ /*
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+ * rk3399 vop big windows register layout is same as rk3288.
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+ */
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+ .win = rk3288_vop_win_data,
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+ .win_size = ARRAY_SIZE(rk3288_vop_win_data),
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};
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-static const struct vop_data rk3036_vop = {
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- .init_table = rk3036_vop_init_reg_table,
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- .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
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- .ctrl = &rk3036_ctrl_data,
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- .intr = &rk3036_intr,
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- .win = rk3036_vop_win_data,
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- .win_size = ARRAY_SIZE(rk3036_vop_win_data),
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+static const struct vop_win_data rk3399_vop_lit_win_data[] = {
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+ { .base = 0x00, .phy = &rk3288_win01_data,
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+ .type = DRM_PLANE_TYPE_PRIMARY },
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+ { .base = 0x00, .phy = &rk3288_win23_data,
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+ .type = DRM_PLANE_TYPE_CURSOR},
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+};
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+
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+static const struct vop_data rk3399_vop_lit = {
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+ .init_table = rk3399_init_reg_table,
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+ .table_size = ARRAY_SIZE(rk3399_init_reg_table),
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+ .intr = &rk3399_vop_intr,
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+ .ctrl = &rk3399_ctrl_data,
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+ /*
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+ * rk3399 vop lit windows register layout is same as rk3288,
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+ * but cut off the win1 and win3 windows.
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+ */
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+ .win = rk3399_vop_lit_win_data,
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+ .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
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};
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static const struct of_device_id vop_driver_dt_match[] = {
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- { .compatible = "rockchip,rk3288-vop",
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- .data = &rk3288_vop },
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{ .compatible = "rockchip,rk3036-vop",
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.data = &rk3036_vop },
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+ { .compatible = "rockchip,rk3288-vop",
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+ .data = &rk3288_vop },
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+ { .compatible = "rockchip,rk3399-vop-big",
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|
|
+ .data = &rk3399_vop_big },
|
|
|
+ { .compatible = "rockchip,rk3399-vop-lit",
|
|
|
+ .data = &rk3399_vop_lit },
|
|
|
{},
|
|
|
};
|
|
|
MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
|