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@@ -9,7 +9,7 @@
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*
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* 7-bit I2C slave address 0x1c/0x1d (pin selectable)
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*
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- * TODO: interrupt, thresholding, orientation / freefall events, autosleep
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+ * TODO: orientation / freefall events, autosleep
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*/
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#include <linux/module.h>
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@@ -18,21 +18,40 @@
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#include <linux/iio/sysfs.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/buffer.h>
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+#include <linux/iio/trigger.h>
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+#include <linux/iio/trigger_consumer.h>
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#include <linux/iio/triggered_buffer.h>
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+#include <linux/iio/events.h>
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#include <linux/delay.h>
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#define MMA8452_STATUS 0x00
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#define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
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#define MMA8452_OUT_Y 0x03
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#define MMA8452_OUT_Z 0x05
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+#define MMA8452_INT_SRC 0x0c
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#define MMA8452_WHO_AM_I 0x0d
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#define MMA8452_DATA_CFG 0x0e
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+#define MMA8452_HP_FILTER_CUTOFF 0x0f
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+#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK (BIT(0) | BIT(1))
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+#define MMA8452_TRANSIENT_CFG 0x1d
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+#define MMA8452_TRANSIENT_CFG_ELE BIT(4)
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+#define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
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+#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
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+#define MMA8452_TRANSIENT_SRC 0x1e
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+#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
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+#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
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+#define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
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+#define MMA8452_TRANSIENT_THS 0x1f
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+#define MMA8452_TRANSIENT_THS_MASK 0x7f
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+#define MMA8452_TRANSIENT_COUNT 0x20
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#define MMA8452_OFF_X 0x2f
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#define MMA8452_OFF_Y 0x30
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#define MMA8452_OFF_Z 0x31
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#define MMA8452_CTRL_REG1 0x2a
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#define MMA8452_CTRL_REG2 0x2b
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#define MMA8452_CTRL_REG2_RST BIT(6)
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+#define MMA8452_CTRL_REG4 0x2d
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+#define MMA8452_CTRL_REG5 0x2e
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#define MMA8452_MAX_REG 0x31
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@@ -47,6 +66,10 @@
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#define MMA8452_DATA_CFG_FS_2G 0
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#define MMA8452_DATA_CFG_FS_4G 1
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#define MMA8452_DATA_CFG_FS_8G 2
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+#define MMA8452_DATA_CFG_HPF_MASK BIT(4)
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+
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+#define MMA8452_INT_DRDY BIT(0)
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+#define MMA8452_INT_TRANS BIT(5)
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#define MMA8452_DEVICE_ID 0x2a
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@@ -109,6 +132,12 @@ static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
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return -EINVAL;
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}
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+static int mma8452_get_odr_index(struct mma8452_data *data)
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+{
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+ return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
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+ MMA8452_CTRL_DR_SHIFT;
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+}
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+
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static const int mma8452_samp_freq[8][2] = {
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{800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
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{6, 250000}, {1, 560000}
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@@ -124,6 +153,30 @@ static const int mma8452_scales[3][2] = {
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{0, 9577}, {0, 19154}, {0, 38307}
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};
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+/* Datasheet table 35 (step time vs sample frequency) */
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+static const int mma8452_transient_time_step_us[8] = {
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+ 1250,
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+ 2500,
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+ 5000,
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+ 10000,
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+ 20000,
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+ 20000,
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+ 20000,
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+ 20000
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+};
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+
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+/* Datasheet table 18 (normal mode) */
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+static const int mma8452_hp_filter_cutoff[8][4][2] = {
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+ { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
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+ { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
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+ { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
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+ { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
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+ { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
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+ { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
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+ { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
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+ { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
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+};
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+
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static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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@@ -138,9 +191,23 @@ static ssize_t mma8452_show_scale_avail(struct device *dev,
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ARRAY_SIZE(mma8452_scales));
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}
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+static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
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+ struct device_attribute *attr,
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+ char *buf)
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+{
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+ struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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+ struct mma8452_data *data = iio_priv(indio_dev);
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+ int i = mma8452_get_odr_index(data);
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+
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+ return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
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+ ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
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+}
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+
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static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
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static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
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mma8452_show_scale_avail, NULL, 0);
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+static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
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+ S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
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static int mma8452_get_samp_freq_index(struct mma8452_data *data,
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int val, int val2)
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@@ -156,6 +223,31 @@ static int mma8452_get_scale_index(struct mma8452_data *data,
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ARRAY_SIZE(mma8452_scales), val, val2);
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}
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+static int mma8452_get_hp_filter_index(struct mma8452_data *data,
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+ int val, int val2)
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+{
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+ int i = mma8452_get_odr_index(data);
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+
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+ return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
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+ ARRAY_SIZE(mma8452_scales[0]), val, val2);
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+}
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+
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+static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
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+{
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+ int i, ret;
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+
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+ ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
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+ if (ret < 0)
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+ return ret;
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+
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+ i = mma8452_get_odr_index(data);
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+ ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
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+ *hz = mma8452_hp_filter_cutoff[i][ret][0];
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+ *uHz = mma8452_hp_filter_cutoff[i][ret][1];
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+
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+ return 0;
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+}
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+
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static int mma8452_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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@@ -183,8 +275,7 @@ static int mma8452_read_raw(struct iio_dev *indio_dev,
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*val2 = mma8452_scales[i][1];
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return IIO_VAL_INT_PLUS_MICRO;
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case IIO_CHAN_INFO_SAMP_FREQ:
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- i = (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
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- MMA8452_CTRL_DR_SHIFT;
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+ i = mma8452_get_odr_index(data);
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*val = mma8452_samp_freq[i][0];
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*val2 = mma8452_samp_freq[i][1];
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return IIO_VAL_INT_PLUS_MICRO;
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@@ -195,6 +286,16 @@ static int mma8452_read_raw(struct iio_dev *indio_dev,
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return ret;
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*val = sign_extend32(ret, 7);
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return IIO_VAL_INT;
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+ case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
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+ if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
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+ ret = mma8452_read_hp_filter(data, val, val2);
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+ if (ret < 0)
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+ return ret;
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+ } else {
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+ *val = 0;
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+ *val2 = 0;
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+ }
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+ return IIO_VAL_INT_PLUS_MICRO;
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}
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return -EINVAL;
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}
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@@ -236,12 +337,31 @@ fail:
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return ret;
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}
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+static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
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+ int val, int val2)
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+{
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+ int i, reg;
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+
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+ i = mma8452_get_hp_filter_index(data, val, val2);
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+ if (i < 0)
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+ return -EINVAL;
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+
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+ reg = i2c_smbus_read_byte_data(data->client,
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+ MMA8452_HP_FILTER_CUTOFF);
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+ if (reg < 0)
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+ return reg;
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+ reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
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+ reg |= i;
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+
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+ return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
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+}
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+
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static int mma8452_write_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int val, int val2, long mask)
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{
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struct mma8452_data *data = iio_priv(indio_dev);
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- int i;
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+ int i, ret;
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if (iio_buffer_enabled(indio_dev))
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return -EBUSY;
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@@ -269,11 +389,217 @@ static int mma8452_write_raw(struct iio_dev *indio_dev,
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return -EINVAL;
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return mma8452_change_config(data, MMA8452_OFF_X +
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chan->scan_index, val);
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+
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+ case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
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+ if (val == 0 && val2 == 0) {
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+ data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
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+ } else {
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+ data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
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+ ret = mma8452_set_hp_filter_frequency(data, val, val2);
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+ if (ret < 0)
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+ return ret;
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+ }
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+ return mma8452_change_config(data, MMA8452_DATA_CFG,
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+ data->data_cfg);
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+
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default:
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return -EINVAL;
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}
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}
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+static int mma8452_read_thresh(struct iio_dev *indio_dev,
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+ const struct iio_chan_spec *chan,
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+ enum iio_event_type type,
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+ enum iio_event_direction dir,
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+ enum iio_event_info info,
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+ int *val, int *val2)
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+{
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+ struct mma8452_data *data = iio_priv(indio_dev);
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+ int ret, us;
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+
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+ switch (info) {
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+ case IIO_EV_INFO_VALUE:
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+ ret = i2c_smbus_read_byte_data(data->client,
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+ MMA8452_TRANSIENT_THS);
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+ if (ret < 0)
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+ return ret;
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+
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+ *val = ret & MMA8452_TRANSIENT_THS_MASK;
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+ return IIO_VAL_INT;
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+
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+ case IIO_EV_INFO_PERIOD:
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+ ret = i2c_smbus_read_byte_data(data->client,
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+ MMA8452_TRANSIENT_COUNT);
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+ if (ret < 0)
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+ return ret;
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+
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+ us = ret * mma8452_transient_time_step_us[
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+ mma8452_get_odr_index(data)];
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+ *val = us / USEC_PER_SEC;
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+ *val2 = us % USEC_PER_SEC;
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+ return IIO_VAL_INT_PLUS_MICRO;
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+
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+ case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
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+ ret = i2c_smbus_read_byte_data(data->client,
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+ MMA8452_TRANSIENT_CFG);
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+ if (ret < 0)
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+ return ret;
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+
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+ if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
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+ *val = 0;
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+ *val2 = 0;
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+ } else {
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+ ret = mma8452_read_hp_filter(data, val, val2);
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+ if (ret < 0)
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+ return ret;
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+ }
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+ return IIO_VAL_INT_PLUS_MICRO;
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+
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+ default:
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+ return -EINVAL;
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+ }
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+}
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+
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+static int mma8452_write_thresh(struct iio_dev *indio_dev,
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+ const struct iio_chan_spec *chan,
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+ enum iio_event_type type,
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+ enum iio_event_direction dir,
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+ enum iio_event_info info,
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+ int val, int val2)
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+{
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+ struct mma8452_data *data = iio_priv(indio_dev);
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+ int ret, reg, steps;
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+
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+ switch (info) {
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+ case IIO_EV_INFO_VALUE:
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+ return mma8452_change_config(data, MMA8452_TRANSIENT_THS,
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+ val & MMA8452_TRANSIENT_THS_MASK);
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+
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+ case IIO_EV_INFO_PERIOD:
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+ steps = (val * USEC_PER_SEC + val2) /
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+ mma8452_transient_time_step_us[
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+ mma8452_get_odr_index(data)];
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+
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+ if (steps > 0xff)
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+ return -EINVAL;
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+
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+ return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT,
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+ steps);
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+ case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
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+ reg = i2c_smbus_read_byte_data(data->client,
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+ MMA8452_TRANSIENT_CFG);
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+ if (reg < 0)
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+ return reg;
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+
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+ if (val == 0 && val2 == 0) {
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+ reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
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+ } else {
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+ reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
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+ ret = mma8452_set_hp_filter_frequency(data, val, val2);
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+ if (ret < 0)
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+ return ret;
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+ }
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+ return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
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+
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+ default:
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+ return -EINVAL;
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+ }
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+}
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+
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+static int mma8452_read_event_config(struct iio_dev *indio_dev,
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+ const struct iio_chan_spec *chan,
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+ enum iio_event_type type,
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+ enum iio_event_direction dir)
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+{
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+ struct mma8452_data *data = iio_priv(indio_dev);
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+ int ret;
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+
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+ ret = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
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+ if (ret < 0)
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+ return ret;
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+
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+ return ret & MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index) ? 1 : 0;
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+}
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+
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+static int mma8452_write_event_config(struct iio_dev *indio_dev,
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+ const struct iio_chan_spec *chan,
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+ enum iio_event_type type,
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+ enum iio_event_direction dir,
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+ int state)
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+{
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+ struct mma8452_data *data = iio_priv(indio_dev);
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+ int val;
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+
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+ val = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG);
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+ if (val < 0)
|
|
|
+ return val;
|
|
|
+
|
|
|
+ if (state)
|
|
|
+ val |= MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
|
|
|
+ else
|
|
|
+ val &= ~MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index);
|
|
|
+
|
|
|
+ val |= MMA8452_TRANSIENT_CFG_ELE;
|
|
|
+
|
|
|
+ return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, val);
|
|
|
+}
|
|
|
+
|
|
|
+static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
|
|
|
+{
|
|
|
+ struct mma8452_data *data = iio_priv(indio_dev);
|
|
|
+ s64 ts = iio_get_time_ns();
|
|
|
+ int src;
|
|
|
+
|
|
|
+ src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
|
|
|
+ if (src < 0)
|
|
|
+ return;
|
|
|
+
|
|
|
+ if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
|
|
|
+ iio_push_event(indio_dev,
|
|
|
+ IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
|
|
|
+ IIO_EV_TYPE_THRESH,
|
|
|
+ IIO_EV_DIR_RISING),
|
|
|
+ ts);
|
|
|
+
|
|
|
+ if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
|
|
|
+ iio_push_event(indio_dev,
|
|
|
+ IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
|
|
|
+ IIO_EV_TYPE_THRESH,
|
|
|
+ IIO_EV_DIR_RISING),
|
|
|
+ ts);
|
|
|
+
|
|
|
+ if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
|
|
|
+ iio_push_event(indio_dev,
|
|
|
+ IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
|
|
|
+ IIO_EV_TYPE_THRESH,
|
|
|
+ IIO_EV_DIR_RISING),
|
|
|
+ ts);
|
|
|
+}
|
|
|
+
|
|
|
+static irqreturn_t mma8452_interrupt(int irq, void *p)
|
|
|
+{
|
|
|
+ struct iio_dev *indio_dev = p;
|
|
|
+ struct mma8452_data *data = iio_priv(indio_dev);
|
|
|
+ int ret = IRQ_NONE;
|
|
|
+ int src;
|
|
|
+
|
|
|
+ src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
|
|
|
+ if (src < 0)
|
|
|
+ return IRQ_NONE;
|
|
|
+
|
|
|
+ if (src & MMA8452_INT_DRDY) {
|
|
|
+ iio_trigger_poll_chained(indio_dev->trig);
|
|
|
+ ret = IRQ_HANDLED;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (src & MMA8452_INT_TRANS) {
|
|
|
+ mma8452_transient_interrupt(indio_dev);
|
|
|
+ ret = IRQ_HANDLED;
|
|
|
+ }
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
static irqreturn_t mma8452_trigger_handler(int irq, void *p)
|
|
|
{
|
|
|
struct iio_poll_func *pf = p;
|
|
@@ -316,6 +642,33 @@ static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
+static const struct iio_event_spec mma8452_transient_event[] = {
|
|
|
+ {
|
|
|
+ .type = IIO_EV_TYPE_THRESH,
|
|
|
+ .dir = IIO_EV_DIR_RISING,
|
|
|
+ .mask_separate = BIT(IIO_EV_INFO_ENABLE),
|
|
|
+ .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
|
|
|
+ BIT(IIO_EV_INFO_PERIOD) |
|
|
|
+ BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * Threshold is configured in fixed 8G/127 steps regardless of
|
|
|
+ * currently selected scale for measurement.
|
|
|
+ */
|
|
|
+static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
|
|
|
+
|
|
|
+static struct attribute *mma8452_event_attributes[] = {
|
|
|
+ &iio_const_attr_accel_transient_scale.dev_attr.attr,
|
|
|
+ NULL,
|
|
|
+};
|
|
|
+
|
|
|
+static struct attribute_group mma8452_event_attribute_group = {
|
|
|
+ .attrs = mma8452_event_attributes,
|
|
|
+ .name = "events",
|
|
|
+};
|
|
|
+
|
|
|
#define MMA8452_CHANNEL(axis, idx) { \
|
|
|
.type = IIO_ACCEL, \
|
|
|
.modified = 1, \
|
|
@@ -323,7 +676,8 @@ static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
|
|
|
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
|
|
|
BIT(IIO_CHAN_INFO_CALIBBIAS), \
|
|
|
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
|
|
|
- BIT(IIO_CHAN_INFO_SCALE), \
|
|
|
+ BIT(IIO_CHAN_INFO_SCALE) | \
|
|
|
+ BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
|
|
|
.scan_index = idx, \
|
|
|
.scan_type = { \
|
|
|
.sign = 's', \
|
|
@@ -332,6 +686,8 @@ static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
|
|
|
.shift = 4, \
|
|
|
.endianness = IIO_BE, \
|
|
|
}, \
|
|
|
+ .event_spec = mma8452_transient_event, \
|
|
|
+ .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
|
|
|
}
|
|
|
|
|
|
static const struct iio_chan_spec mma8452_channels[] = {
|
|
@@ -344,6 +700,7 @@ static const struct iio_chan_spec mma8452_channels[] = {
|
|
|
static struct attribute *mma8452_attributes[] = {
|
|
|
&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
|
|
|
&iio_dev_attr_in_accel_scale_available.dev_attr.attr,
|
|
|
+ &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
|
|
|
NULL
|
|
|
};
|
|
|
|
|
@@ -355,12 +712,83 @@ static const struct iio_info mma8452_info = {
|
|
|
.attrs = &mma8452_group,
|
|
|
.read_raw = &mma8452_read_raw,
|
|
|
.write_raw = &mma8452_write_raw,
|
|
|
+ .event_attrs = &mma8452_event_attribute_group,
|
|
|
+ .read_event_value = &mma8452_read_thresh,
|
|
|
+ .write_event_value = &mma8452_write_thresh,
|
|
|
+ .read_event_config = &mma8452_read_event_config,
|
|
|
+ .write_event_config = &mma8452_write_event_config,
|
|
|
.debugfs_reg_access = &mma8452_reg_access_dbg,
|
|
|
.driver_module = THIS_MODULE,
|
|
|
};
|
|
|
|
|
|
static const unsigned long mma8452_scan_masks[] = {0x7, 0};
|
|
|
|
|
|
+static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
|
|
|
+ bool state)
|
|
|
+{
|
|
|
+ struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
|
|
|
+ struct mma8452_data *data = iio_priv(indio_dev);
|
|
|
+ int reg;
|
|
|
+
|
|
|
+ reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
|
|
|
+ if (reg < 0)
|
|
|
+ return reg;
|
|
|
+
|
|
|
+ if (state)
|
|
|
+ reg |= MMA8452_INT_DRDY;
|
|
|
+ else
|
|
|
+ reg &= ~MMA8452_INT_DRDY;
|
|
|
+
|
|
|
+ return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
|
|
|
+}
|
|
|
+
|
|
|
+static int mma8452_validate_device(struct iio_trigger *trig,
|
|
|
+ struct iio_dev *indio_dev)
|
|
|
+{
|
|
|
+ struct iio_dev *indio = iio_trigger_get_drvdata(trig);
|
|
|
+
|
|
|
+ if (indio != indio_dev)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct iio_trigger_ops mma8452_trigger_ops = {
|
|
|
+ .set_trigger_state = mma8452_data_rdy_trigger_set_state,
|
|
|
+ .validate_device = mma8452_validate_device,
|
|
|
+ .owner = THIS_MODULE,
|
|
|
+};
|
|
|
+
|
|
|
+static int mma8452_trigger_setup(struct iio_dev *indio_dev)
|
|
|
+{
|
|
|
+ struct mma8452_data *data = iio_priv(indio_dev);
|
|
|
+ struct iio_trigger *trig;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
|
|
|
+ indio_dev->name,
|
|
|
+ indio_dev->id);
|
|
|
+ if (!trig)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ trig->dev.parent = &data->client->dev;
|
|
|
+ trig->ops = &mma8452_trigger_ops;
|
|
|
+ iio_trigger_set_drvdata(trig, indio_dev);
|
|
|
+
|
|
|
+ ret = iio_trigger_register(trig);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ indio_dev->trig = trig;
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
|
|
|
+{
|
|
|
+ if (indio_dev->trig)
|
|
|
+ iio_trigger_unregister(indio_dev->trig);
|
|
|
+}
|
|
|
+
|
|
|
static int mma8452_reset(struct i2c_client *client)
|
|
|
{
|
|
|
int i;
|
|
@@ -425,25 +853,77 @@ static int mma8452_probe(struct i2c_client *client,
|
|
|
if (ret < 0)
|
|
|
return ret;
|
|
|
|
|
|
+ /*
|
|
|
+ * By default set transient threshold to max to avoid events if
|
|
|
+ * enabling without configuring threshold.
|
|
|
+ */
|
|
|
+ ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
|
|
|
+ MMA8452_TRANSIENT_THS_MASK);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ if (client->irq) {
|
|
|
+ /*
|
|
|
+ * Although we enable the transient interrupt source once and
|
|
|
+ * for all here the transient event detection itself is not
|
|
|
+ * enabled until userspace asks for it by
|
|
|
+ * mma8452_write_event_config()
|
|
|
+ */
|
|
|
+ int supported_interrupts = MMA8452_INT_DRDY | MMA8452_INT_TRANS;
|
|
|
+ int enabled_interrupts = MMA8452_INT_TRANS;
|
|
|
+
|
|
|
+ /* Assume wired to INT1 pin */
|
|
|
+ ret = i2c_smbus_write_byte_data(client,
|
|
|
+ MMA8452_CTRL_REG5,
|
|
|
+ supported_interrupts);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = i2c_smbus_write_byte_data(client,
|
|
|
+ MMA8452_CTRL_REG4,
|
|
|
+ enabled_interrupts);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = mma8452_trigger_setup(indio_dev);
|
|
|
+ if (ret < 0)
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
|
|
|
(MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
|
|
|
ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
|
|
|
data->ctrl_reg1);
|
|
|
if (ret < 0)
|
|
|
- return ret;
|
|
|
+ goto trigger_cleanup;
|
|
|
|
|
|
ret = iio_triggered_buffer_setup(indio_dev, NULL,
|
|
|
mma8452_trigger_handler, NULL);
|
|
|
if (ret < 0)
|
|
|
- return ret;
|
|
|
+ goto trigger_cleanup;
|
|
|
+
|
|
|
+ if (client->irq) {
|
|
|
+ ret = devm_request_threaded_irq(&client->dev,
|
|
|
+ client->irq,
|
|
|
+ NULL, mma8452_interrupt,
|
|
|
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
|
|
|
+ client->name, indio_dev);
|
|
|
+ if (ret)
|
|
|
+ goto buffer_cleanup;
|
|
|
+ }
|
|
|
|
|
|
ret = iio_device_register(indio_dev);
|
|
|
if (ret < 0)
|
|
|
goto buffer_cleanup;
|
|
|
+
|
|
|
return 0;
|
|
|
|
|
|
buffer_cleanup:
|
|
|
iio_triggered_buffer_cleanup(indio_dev);
|
|
|
+
|
|
|
+trigger_cleanup:
|
|
|
+ mma8452_trigger_cleanup(indio_dev);
|
|
|
+
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
@@ -453,6 +933,7 @@ static int mma8452_remove(struct i2c_client *client)
|
|
|
|
|
|
iio_device_unregister(indio_dev);
|
|
|
iio_triggered_buffer_cleanup(indio_dev);
|
|
|
+ mma8452_trigger_cleanup(indio_dev);
|
|
|
mma8452_standby(iio_priv(indio_dev));
|
|
|
|
|
|
return 0;
|