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@@ -31,92 +31,15 @@
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#include <sound/initval.h>
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#include "hda_controller.h"
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-#define CREATE_TRACE_POINTS
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-#include "hda_intel_trace.h"
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-
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/* DSP lock helpers */
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-#ifdef CONFIG_SND_HDA_DSP_LOADER
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-#define dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
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-#define dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
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-#define dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
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-#define dsp_is_locked(dev) ((dev)->locked)
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-#else
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-#define dsp_lock_init(dev) do {} while (0)
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-#define dsp_lock(dev) do {} while (0)
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-#define dsp_unlock(dev) do {} while (0)
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-#define dsp_is_locked(dev) 0
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-#endif
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+#define dsp_lock(dev) snd_hdac_dsp_lock(azx_stream(dev))
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+#define dsp_unlock(dev) snd_hdac_dsp_unlock(azx_stream(dev))
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+#define dsp_is_locked(dev) snd_hdac_stream_is_locked(azx_stream(dev))
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/*
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* AZX stream operations.
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*/
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-/* start a stream */
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-static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
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-{
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- /*
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- * Before stream start, initialize parameter
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- */
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- azx_dev->insufficient = 1;
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-
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- /* enable SIE */
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- azx_writel(chip, INTCTL,
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- azx_readl(chip, INTCTL) | (1 << azx_dev->index));
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- /* set DMA start and interrupt mask */
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- azx_sd_writeb(chip, azx_dev, SD_CTL,
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- azx_sd_readb(chip, azx_dev, SD_CTL) |
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- SD_CTL_DMA_START | SD_INT_MASK);
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-}
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-
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-/* stop DMA */
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-static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
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-{
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- azx_sd_writeb(chip, azx_dev, SD_CTL,
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- azx_sd_readb(chip, azx_dev, SD_CTL) &
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- ~(SD_CTL_DMA_START | SD_INT_MASK));
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- azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
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-}
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-
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-/* stop a stream */
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-void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
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-{
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- azx_stream_clear(chip, azx_dev);
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- /* disable SIE */
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- azx_writel(chip, INTCTL,
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- azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
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-}
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-EXPORT_SYMBOL_GPL(azx_stream_stop);
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-
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-/* reset stream */
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-static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
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-{
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- unsigned char val;
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- int timeout;
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-
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- azx_stream_clear(chip, azx_dev);
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-
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- azx_sd_writeb(chip, azx_dev, SD_CTL,
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- azx_sd_readb(chip, azx_dev, SD_CTL) |
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- SD_CTL_STREAM_RESET);
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- udelay(3);
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- timeout = 300;
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- while (!((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
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- SD_CTL_STREAM_RESET) && --timeout)
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- ;
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- val &= ~SD_CTL_STREAM_RESET;
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- azx_sd_writeb(chip, azx_dev, SD_CTL, val);
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- udelay(3);
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-
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- timeout = 300;
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- /* waiting for hardware to report that the stream is out of reset */
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- while (((val = azx_sd_readb(chip, azx_dev, SD_CTL)) &
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- SD_CTL_STREAM_RESET) && --timeout)
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- ;
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-
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- /* reset first position - may not be synced with hw at this time */
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- *azx_dev->posbuf = 0;
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-}
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-
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/*
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* set up the SD for streaming
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*/
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@@ -124,31 +47,31 @@ static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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{
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unsigned int val;
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/* make sure the run bit is zero for SD */
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- azx_stream_clear(chip, azx_dev);
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+ snd_hdac_stream_clear(azx_stream(azx_dev));
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/* program the stream_tag */
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val = azx_sd_readl(chip, azx_dev, SD_CTL);
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val = (val & ~SD_CTL_STREAM_TAG_MASK) |
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- (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
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+ (azx_dev->core.stream_tag << SD_CTL_STREAM_TAG_SHIFT);
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if (!azx_snoop(chip))
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val |= SD_CTL_TRAFFIC_PRIO;
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azx_sd_writel(chip, azx_dev, SD_CTL, val);
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/* program the length of samples in cyclic buffer */
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- azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->bufsize);
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+ azx_sd_writel(chip, azx_dev, SD_CBL, azx_dev->core.bufsize);
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/* program the stream format */
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/* this value needs to be the same as the one programmed */
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- azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->format_val);
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+ azx_sd_writew(chip, azx_dev, SD_FORMAT, azx_dev->core.format_val);
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/* program the stream LVI (last valid index) of the BDL */
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- azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->frags - 1);
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+ azx_sd_writew(chip, azx_dev, SD_LVI, azx_dev->core.frags - 1);
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/* program the BDL address */
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/* lower BDL address */
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- azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
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+ azx_sd_writel(chip, azx_dev, SD_BDLPL, (u32)azx_dev->core.bdl.addr);
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/* upper BDL address */
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azx_sd_writel(chip, azx_dev, SD_BDLPU,
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- upper_32_bits(azx_dev->bdl.addr));
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+ upper_32_bits(azx_dev->core.bdl.addr));
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/* enable the position buffer */
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if (chip->get_position[0] != azx_get_pos_lpib ||
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@@ -169,54 +92,24 @@ static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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static inline struct azx_dev *
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azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
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{
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- int dev, i, nums;
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- struct azx_dev *res = NULL;
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- /* make a non-zero unique key for the substream */
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- int key = (substream->pcm->device << 16) | (substream->number << 2) |
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- (substream->stream + 1);
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-
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- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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- dev = chip->playback_index_offset;
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- nums = chip->playback_streams;
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- } else {
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- dev = chip->capture_index_offset;
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- nums = chip->capture_streams;
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- }
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- for (i = 0; i < nums; i++, dev++) {
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- struct azx_dev *azx_dev = &chip->azx_dev[dev];
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- dsp_lock(azx_dev);
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- if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
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- if (azx_dev->assigned_key == key) {
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- azx_dev->opened = 1;
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- azx_dev->assigned_key = key;
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- dsp_unlock(azx_dev);
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- return azx_dev;
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- }
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- if (!res ||
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- (chip->driver_caps & AZX_DCAPS_REVERSE_ASSIGN))
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- res = azx_dev;
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- }
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- dsp_unlock(azx_dev);
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- }
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- if (res) {
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- dsp_lock(res);
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- res->opened = 1;
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- res->assigned_key = key;
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- dsp_unlock(res);
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- }
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- return res;
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+ struct hdac_stream *s;
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+
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+ s = snd_hdac_stream_assign(azx_bus(chip), substream);
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+ if (!s)
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+ return NULL;
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+ return stream_to_azx_dev(s);
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}
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/* release the assigned stream */
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static inline void azx_release_device(struct azx_dev *azx_dev)
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{
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- azx_dev->opened = 0;
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+ snd_hdac_stream_release(azx_stream(azx_dev));
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}
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static cycle_t azx_cc_read(const struct cyclecounter *cc)
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{
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- struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
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- struct snd_pcm_substream *substream = azx_dev->substream;
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+ struct azx_dev *azx_dev = container_of(cc, struct azx_dev, core.cc);
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+ struct snd_pcm_substream *substream = azx_dev->core.substream;
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struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
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struct azx *chip = apcm->chip;
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@@ -227,8 +120,8 @@ static void azx_timecounter_init(struct snd_pcm_substream *substream,
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bool force, cycle_t last)
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{
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struct azx_dev *azx_dev = get_azx_dev(substream);
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- struct timecounter *tc = &azx_dev->azx_tc;
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- struct cyclecounter *cc = &azx_dev->azx_cc;
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+ struct timecounter *tc = &azx_dev->core.tc;
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+ struct cyclecounter *cc = &azx_dev->core.cc;
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u64 nsec;
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cc->read = azx_cc_read;
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@@ -298,7 +191,7 @@ static int setup_bdle(struct azx *chip,
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dma_addr_t addr;
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int chunk;
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- if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
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+ if (azx_dev->core.frags >= AZX_MAX_BDL_ENTRIES)
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return -EINVAL;
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addr = snd_sgbuf_get_addr(dmab, ofs);
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@@ -320,7 +213,7 @@ static int setup_bdle(struct azx *chip,
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size -= chunk;
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bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
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bdl += 4;
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- azx_dev->frags++;
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+ azx_dev->core.frags++;
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ofs += chunk;
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}
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*bdlp = bdl;
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@@ -342,17 +235,17 @@ static int azx_setup_periods(struct azx *chip,
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azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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- period_bytes = azx_dev->period_bytes;
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- periods = azx_dev->bufsize / period_bytes;
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+ period_bytes = azx_dev->core.period_bytes;
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+ periods = azx_dev->core.bufsize / period_bytes;
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/* program the initial BDL entries */
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- bdl = (u32 *)azx_dev->bdl.area;
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+ bdl = (u32 *)azx_dev->core.bdl.area;
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ofs = 0;
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- azx_dev->frags = 0;
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+ azx_dev->core.frags = 0;
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if (chip->bdl_pos_adj)
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pos_adj = chip->bdl_pos_adj[chip->dev_index];
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- if (!azx_dev->no_period_wakeup && pos_adj > 0) {
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+ if (!azx_dev->core.no_period_wakeup && pos_adj > 0) {
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struct snd_pcm_runtime *runtime = substream->runtime;
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int pos_align = pos_adj;
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pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
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@@ -385,7 +278,7 @@ static int azx_setup_periods(struct azx *chip,
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ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
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azx_dev, &bdl, ofs,
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period_bytes,
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- !azx_dev->no_period_wakeup);
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+ !azx_dev->core.no_period_wakeup);
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if (ofs < 0)
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goto error;
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}
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@@ -393,7 +286,7 @@ static int azx_setup_periods(struct azx *chip,
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error:
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dev_err(chip->card->dev, "Too many BDL entries: buffer=%d, period=%d\n",
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- azx_dev->bufsize, period_bytes);
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+ azx_dev->core.bufsize, period_bytes);
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return -EINVAL;
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}
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@@ -411,8 +304,8 @@ static int azx_pcm_close(struct snd_pcm_substream *substream)
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mutex_lock(&chip->open_mutex);
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spin_lock_irqsave(&chip->reg_lock, flags);
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- azx_dev->substream = NULL;
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- azx_dev->running = 0;
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+ azx_dev->core.substream = NULL;
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+ azx_dev->core.running = 0;
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spin_unlock_irqrestore(&chip->reg_lock, flags);
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azx_release_device(azx_dev);
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if (hinfo->ops.close)
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@@ -457,9 +350,9 @@ static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
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azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
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azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
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azx_sd_writel(chip, azx_dev, SD_CTL, 0);
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- azx_dev->bufsize = 0;
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- azx_dev->period_bytes = 0;
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- azx_dev->format_val = 0;
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+ azx_dev->core.bufsize = 0;
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+ azx_dev->core.period_bytes = 0;
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+ azx_dev->core.format_val = 0;
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}
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snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
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@@ -489,7 +382,7 @@ static int azx_pcm_prepare(struct snd_pcm_substream *substream)
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goto unlock;
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}
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- azx_stream_reset(chip, azx_dev);
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+ snd_hdac_stream_reset(azx_stream(azx_dev));
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format_val = snd_hda_calc_stream_format(apcm->codec,
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runtime->rate,
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runtime->channels,
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@@ -510,14 +403,14 @@ static int azx_pcm_prepare(struct snd_pcm_substream *substream)
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dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
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bufsize, format_val);
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- if (bufsize != azx_dev->bufsize ||
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- period_bytes != azx_dev->period_bytes ||
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- format_val != azx_dev->format_val ||
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- runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
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- azx_dev->bufsize = bufsize;
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- azx_dev->period_bytes = period_bytes;
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- azx_dev->format_val = format_val;
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- azx_dev->no_period_wakeup = runtime->no_period_wakeup;
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+ if (bufsize != azx_dev->core.bufsize ||
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+ period_bytes != azx_dev->core.period_bytes ||
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+ format_val != azx_dev->core.format_val ||
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+ runtime->no_period_wakeup != azx_dev->core.no_period_wakeup) {
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+ azx_dev->core.bufsize = bufsize;
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+ azx_dev->core.period_bytes = period_bytes;
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+ azx_dev->core.format_val = format_val;
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+ azx_dev->core.no_period_wakeup = runtime->no_period_wakeup;
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err = azx_setup_periods(chip, substream, azx_dev);
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if (err < 0)
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goto unlock;
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@@ -528,27 +421,27 @@ static int azx_pcm_prepare(struct snd_pcm_substream *substream)
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* 64 frames
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*/
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if (runtime->period_size > 64)
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- azx_dev->delay_negative_threshold = -frames_to_bytes(runtime, 64);
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+ azx_dev->core.delay_negative_threshold = -frames_to_bytes(runtime, 64);
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else
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- azx_dev->delay_negative_threshold = 0;
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+ azx_dev->core.delay_negative_threshold = 0;
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/* wallclk has 24Mhz clock source */
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- azx_dev->period_wallclk = (((runtime->period_size * 24000) /
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+ azx_dev->core.period_wallclk = (((runtime->period_size * 24000) /
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runtime->rate) * 1000);
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azx_setup_controller(chip, azx_dev);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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- azx_dev->fifo_size =
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+ azx_dev->core.fifo_size =
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azx_sd_readw(chip, azx_dev, SD_FIFOSIZE) + 1;
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else
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- azx_dev->fifo_size = 0;
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+ azx_dev->core.fifo_size = 0;
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- stream_tag = azx_dev->stream_tag;
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+ stream_tag = azx_dev->core.stream_tag;
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/* CA-IBG chips need the playback stream starting from 1 */
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if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
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stream_tag > chip->capture_streams)
|
|
|
stream_tag -= chip->capture_streams;
|
|
|
err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
|
|
|
- azx_dev->format_val, substream);
|
|
|
+ azx_dev->core.format_val, substream);
|
|
|
|
|
|
unlock:
|
|
|
if (!err)
|
|
@@ -567,7 +460,6 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
|
int nwait, timeout;
|
|
|
|
|
|
azx_dev = get_azx_dev(substream);
|
|
|
- trace_azx_pcm_trigger(chip, azx_dev, cmd);
|
|
|
|
|
|
if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
|
|
|
return -EPIPE;
|
|
@@ -592,7 +484,7 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
|
if (s->pcm->card != substream->pcm->card)
|
|
|
continue;
|
|
|
azx_dev = get_azx_dev(s);
|
|
|
- sbits |= 1 << azx_dev->index;
|
|
|
+ sbits |= 1 << azx_dev->core.index;
|
|
|
nsync++;
|
|
|
snd_pcm_trigger_done(s, substream);
|
|
|
}
|
|
@@ -611,15 +503,11 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
|
continue;
|
|
|
azx_dev = get_azx_dev(s);
|
|
|
if (start) {
|
|
|
- azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
|
|
|
- if (!rstart)
|
|
|
- azx_dev->start_wallclk -=
|
|
|
- azx_dev->period_wallclk;
|
|
|
- azx_stream_start(chip, azx_dev);
|
|
|
+ azx_dev->insufficient = 1;
|
|
|
+ snd_hdac_stream_start(azx_stream(azx_dev), true);
|
|
|
} else {
|
|
|
- azx_stream_stop(chip, azx_dev);
|
|
|
+ snd_hdac_stream_stop(azx_stream(azx_dev));
|
|
|
}
|
|
|
- azx_dev->running = start;
|
|
|
}
|
|
|
spin_unlock(&chip->reg_lock);
|
|
|
if (start) {
|
|
@@ -672,7 +560,7 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
|
|
|
|
/* same start cycle for master and group */
|
|
|
azx_dev = get_azx_dev(substream);
|
|
|
- cycle_last = azx_dev->azx_tc.cycle_last;
|
|
|
+ cycle_last = azx_dev->core.tc.cycle_last;
|
|
|
|
|
|
snd_pcm_group_for_each_entry(s, substream) {
|
|
|
if (s->pcm->card != substream->pcm->card)
|
|
@@ -687,20 +575,20 @@ static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
|
|
|
|
|
|
unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
|
|
|
{
|
|
|
- return azx_sd_readl(chip, azx_dev, SD_LPIB);
|
|
|
+ return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
|
|
|
}
|
|
|
EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
|
|
|
|
|
|
unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
|
|
|
{
|
|
|
- return le32_to_cpu(*azx_dev->posbuf);
|
|
|
+ return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
|
|
|
}
|
|
|
EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
|
|
|
|
|
|
unsigned int azx_get_position(struct azx *chip,
|
|
|
struct azx_dev *azx_dev)
|
|
|
{
|
|
|
- struct snd_pcm_substream *substream = azx_dev->substream;
|
|
|
+ struct snd_pcm_substream *substream = azx_dev->core.substream;
|
|
|
unsigned int pos;
|
|
|
int stream = substream->stream;
|
|
|
int delay = 0;
|
|
@@ -710,7 +598,7 @@ unsigned int azx_get_position(struct azx *chip,
|
|
|
else /* use the position buffer as default */
|
|
|
pos = azx_get_pos_posbuf(chip, azx_dev);
|
|
|
|
|
|
- if (pos >= azx_dev->bufsize)
|
|
|
+ if (pos >= azx_dev->core.bufsize)
|
|
|
pos = 0;
|
|
|
|
|
|
if (substream->runtime) {
|
|
@@ -725,7 +613,6 @@ unsigned int azx_get_position(struct azx *chip,
|
|
|
substream->runtime->delay = delay;
|
|
|
}
|
|
|
|
|
|
- trace_azx_get_position(chip, azx_dev, pos, delay);
|
|
|
return pos;
|
|
|
}
|
|
|
EXPORT_SYMBOL_GPL(azx_get_position);
|
|
@@ -752,7 +639,7 @@ static int azx_get_time_info(struct snd_pcm_substream *substream,
|
|
|
|
|
|
snd_pcm_gettime(substream->runtime, system_ts);
|
|
|
|
|
|
- nsec = timecounter_read(&azx_dev->azx_tc);
|
|
|
+ nsec = timecounter_read(&azx_dev->core.tc);
|
|
|
nsec = div_u64(nsec, 3); /* can be optimized */
|
|
|
if (audio_tstamp_config->report_delay)
|
|
|
nsec = azx_adjust_codec_delay(substream, nsec);
|
|
@@ -875,8 +762,8 @@ static int azx_pcm_open(struct snd_pcm_substream *substream)
|
|
|
}
|
|
|
|
|
|
spin_lock_irqsave(&chip->reg_lock, flags);
|
|
|
- azx_dev->substream = substream;
|
|
|
- azx_dev->running = 0;
|
|
|
+ azx_dev->core.substream = substream;
|
|
|
+ azx_dev->core.running = 0;
|
|
|
spin_unlock_irqrestore(&chip->reg_lock, flags);
|
|
|
|
|
|
runtime->private_data = azx_dev;
|
|
@@ -1370,7 +1257,14 @@ static const struct hdac_bus_ops bus_core_ops = {
|
|
|
static struct azx_dev *
|
|
|
azx_get_dsp_loader_dev(struct azx *chip)
|
|
|
{
|
|
|
- return &chip->azx_dev[chip->playback_index_offset];
|
|
|
+ struct hdac_bus *bus = azx_bus(chip);
|
|
|
+ struct hdac_stream *s;
|
|
|
+
|
|
|
+ list_for_each_entry(s, &bus->stream_list, list)
|
|
|
+ if (s->index == chip->playback_index_offset)
|
|
|
+ return stream_to_azx_dev(s);
|
|
|
+
|
|
|
+ return NULL;
|
|
|
}
|
|
|
|
|
|
static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
|
|
@@ -1386,14 +1280,14 @@ static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
|
|
|
|
|
|
dsp_lock(azx_dev);
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
|
- if (azx_dev->running || azx_dev->locked) {
|
|
|
+ if (azx_dev->core.running || azx_dev->core.locked) {
|
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
err = -EBUSY;
|
|
|
goto unlock;
|
|
|
}
|
|
|
azx_dev->prepared = 0;
|
|
|
chip->saved_azx_dev = *azx_dev;
|
|
|
- azx_dev->locked = 1;
|
|
|
+ azx_dev->core.locked = 1;
|
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
|
|
|
err = chip->io_ops->dma_alloc_pages(&bus->core, SNDRV_DMA_TYPE_DEV_SG,
|
|
@@ -1401,33 +1295,33 @@ static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
|
|
|
if (err < 0)
|
|
|
goto err_alloc;
|
|
|
|
|
|
- azx_dev->bufsize = byte_size;
|
|
|
- azx_dev->period_bytes = byte_size;
|
|
|
- azx_dev->format_val = format;
|
|
|
+ azx_dev->core.bufsize = byte_size;
|
|
|
+ azx_dev->core.period_bytes = byte_size;
|
|
|
+ azx_dev->core.format_val = format;
|
|
|
|
|
|
- azx_stream_reset(chip, azx_dev);
|
|
|
+ snd_hdac_stream_reset(azx_stream(azx_dev));
|
|
|
|
|
|
/* reset BDL address */
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
|
|
|
|
|
|
- azx_dev->frags = 0;
|
|
|
- bdl = (u32 *)azx_dev->bdl.area;
|
|
|
+ azx_dev->core.frags = 0;
|
|
|
+ bdl = (u32 *)azx_dev->core.bdl.area;
|
|
|
err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
|
|
|
if (err < 0)
|
|
|
goto error;
|
|
|
|
|
|
azx_setup_controller(chip, azx_dev);
|
|
|
dsp_unlock(azx_dev);
|
|
|
- return azx_dev->stream_tag;
|
|
|
+ return azx_dev->core.stream_tag;
|
|
|
|
|
|
error:
|
|
|
chip->io_ops->dma_free_pages(&bus->core, bufp);
|
|
|
err_alloc:
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
|
- if (azx_dev->opened)
|
|
|
+ if (azx_dev->core.opened)
|
|
|
*azx_dev = chip->saved_azx_dev;
|
|
|
- azx_dev->locked = 0;
|
|
|
+ azx_dev->core.locked = 0;
|
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
unlock:
|
|
|
dsp_unlock(azx_dev);
|
|
@@ -1440,10 +1334,9 @@ static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
|
|
|
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
|
|
|
|
|
|
if (start)
|
|
|
- azx_stream_start(chip, azx_dev);
|
|
|
+ snd_hdac_stream_start(azx_stream(azx_dev), false);
|
|
|
else
|
|
|
- azx_stream_stop(chip, azx_dev);
|
|
|
- azx_dev->running = start;
|
|
|
+ snd_hdac_stream_stop(azx_stream(azx_dev));
|
|
|
}
|
|
|
|
|
|
static void azx_load_dsp_cleanup(struct hda_bus *bus,
|
|
@@ -1452,7 +1345,7 @@ static void azx_load_dsp_cleanup(struct hda_bus *bus,
|
|
|
struct azx *chip = bus->private_data;
|
|
|
struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
|
|
|
|
|
|
- if (!dmab->area || !azx_dev->locked)
|
|
|
+ if (!dmab->area || !azx_dev->core.locked)
|
|
|
return;
|
|
|
|
|
|
dsp_lock(azx_dev);
|
|
@@ -1460,17 +1353,17 @@ static void azx_load_dsp_cleanup(struct hda_bus *bus,
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
|
|
|
azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
|
|
|
azx_sd_writel(chip, azx_dev, SD_CTL, 0);
|
|
|
- azx_dev->bufsize = 0;
|
|
|
- azx_dev->period_bytes = 0;
|
|
|
- azx_dev->format_val = 0;
|
|
|
+ azx_dev->core.bufsize = 0;
|
|
|
+ azx_dev->core.period_bytes = 0;
|
|
|
+ azx_dev->core.format_val = 0;
|
|
|
|
|
|
chip->io_ops->dma_free_pages(&bus->core, dmab);
|
|
|
dmab->area = NULL;
|
|
|
|
|
|
spin_lock_irq(&chip->reg_lock);
|
|
|
- if (azx_dev->opened)
|
|
|
+ if (azx_dev->core.opened)
|
|
|
*azx_dev = chip->saved_azx_dev;
|
|
|
- azx_dev->locked = 0;
|
|
|
+ azx_dev->core.locked = 0;
|
|
|
spin_unlock_irq(&chip->reg_lock);
|
|
|
dsp_unlock(azx_dev);
|
|
|
}
|
|
@@ -1478,17 +1371,18 @@ static void azx_load_dsp_cleanup(struct hda_bus *bus,
|
|
|
|
|
|
int azx_alloc_stream_pages(struct azx *chip)
|
|
|
{
|
|
|
- int i, err;
|
|
|
+ struct hdac_bus *bus = azx_bus(chip);
|
|
|
+ struct hdac_stream *s;
|
|
|
+ int err;
|
|
|
|
|
|
- for (i = 0; i < chip->num_streams; i++) {
|
|
|
- dsp_lock_init(&chip->azx_dev[i]);
|
|
|
+ list_for_each_entry(s, &bus->stream_list, list) {
|
|
|
/* allocate memory for the BDL for each stream */
|
|
|
err = chip->io_ops->dma_alloc_pages(azx_bus(chip), SNDRV_DMA_TYPE_DEV,
|
|
|
- BDL_SIZE,
|
|
|
- &chip->azx_dev[i].bdl);
|
|
|
+ BDL_SIZE, &s->bdl);
|
|
|
if (err < 0)
|
|
|
return -ENOMEM;
|
|
|
}
|
|
|
+
|
|
|
/* allocate memory for the position buffer */
|
|
|
err = chip->io_ops->dma_alloc_pages(azx_bus(chip), SNDRV_DMA_TYPE_DEV,
|
|
|
chip->num_streams * 8, &chip->posbuf);
|
|
@@ -1505,13 +1399,15 @@ EXPORT_SYMBOL_GPL(azx_alloc_stream_pages);
|
|
|
|
|
|
void azx_free_stream_pages(struct azx *chip)
|
|
|
{
|
|
|
- int i;
|
|
|
- if (chip->azx_dev) {
|
|
|
- for (i = 0; i < chip->num_streams; i++)
|
|
|
- if (chip->azx_dev[i].bdl.area)
|
|
|
- chip->io_ops->dma_free_pages(azx_bus(chip),
|
|
|
- &chip->azx_dev[i].bdl);
|
|
|
+ struct hdac_bus *bus = azx_bus(chip);
|
|
|
+ struct hdac_stream *s, *next;
|
|
|
+
|
|
|
+ list_for_each_entry_safe(s, next, &bus->stream_list, list) {
|
|
|
+ if (s->bdl.area)
|
|
|
+ chip->io_ops->dma_free_pages(azx_bus(chip), &s->bdl);
|
|
|
+ kfree(s);
|
|
|
}
|
|
|
+
|
|
|
if (chip->rb.area)
|
|
|
chip->io_ops->dma_free_pages(azx_bus(chip), &chip->rb);
|
|
|
if (chip->posbuf.area)
|
|
@@ -1607,15 +1503,12 @@ static void azx_int_enable(struct azx *chip)
|
|
|
/* disable interrupts */
|
|
|
static void azx_int_disable(struct azx *chip)
|
|
|
{
|
|
|
- int i;
|
|
|
+ struct hdac_bus *bus = azx_bus(chip);
|
|
|
+ struct hdac_stream *s;
|
|
|
|
|
|
/* disable interrupts in stream descriptor */
|
|
|
- for (i = 0; i < chip->num_streams; i++) {
|
|
|
- struct azx_dev *azx_dev = &chip->azx_dev[i];
|
|
|
- azx_sd_writeb(chip, azx_dev, SD_CTL,
|
|
|
- azx_sd_readb(chip, azx_dev, SD_CTL) &
|
|
|
- ~SD_INT_MASK);
|
|
|
- }
|
|
|
+ list_for_each_entry(s, &bus->stream_list, list)
|
|
|
+ snd_hdac_stream_updateb(s, SD_CTL, SD_INT_MASK, 0);
|
|
|
|
|
|
/* disable SIE for all streams */
|
|
|
azx_writeb(chip, INTCTL, 0);
|
|
@@ -1628,13 +1521,12 @@ static void azx_int_disable(struct azx *chip)
|
|
|
/* clear interrupts */
|
|
|
static void azx_int_clear(struct azx *chip)
|
|
|
{
|
|
|
- int i;
|
|
|
+ struct hdac_bus *bus = azx_bus(chip);
|
|
|
+ struct hdac_stream *s;
|
|
|
|
|
|
/* clear stream status */
|
|
|
- for (i = 0; i < chip->num_streams; i++) {
|
|
|
- struct azx_dev *azx_dev = &chip->azx_dev[i];
|
|
|
- azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
|
|
|
- }
|
|
|
+ list_for_each_entry(s, &bus->stream_list, list)
|
|
|
+ snd_hdac_stream_writeb(s, SD_STS, SD_INT_MASK);
|
|
|
|
|
|
/* clear STATESTS */
|
|
|
azx_writew(chip, STATESTS, STATESTS_INT_MASK);
|
|
@@ -1673,6 +1565,16 @@ void azx_init_chip(struct azx *chip, bool full_reset)
|
|
|
}
|
|
|
EXPORT_SYMBOL_GPL(azx_init_chip);
|
|
|
|
|
|
+void azx_stop_all_streams(struct azx *chip)
|
|
|
+{
|
|
|
+ struct hdac_bus *bus = azx_bus(chip);
|
|
|
+ struct hdac_stream *s;
|
|
|
+
|
|
|
+ list_for_each_entry(s, &bus->stream_list, list)
|
|
|
+ snd_hdac_stream_stop(s);
|
|
|
+}
|
|
|
+EXPORT_SYMBOL_GPL(azx_stop_all_streams);
|
|
|
+
|
|
|
void azx_stop_chip(struct azx *chip)
|
|
|
{
|
|
|
if (!chip->initialized)
|
|
@@ -1696,13 +1598,26 @@ EXPORT_SYMBOL_GPL(azx_stop_chip);
|
|
|
/*
|
|
|
* interrupt handler
|
|
|
*/
|
|
|
+static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
|
|
|
+{
|
|
|
+ struct hda_bus *hbus = container_of(bus, struct hda_bus, core);
|
|
|
+ struct azx *chip = hbus->private_data;
|
|
|
+ struct azx_dev *azx_dev = stream_to_azx_dev(s);
|
|
|
+
|
|
|
+ /* check whether this IRQ is really acceptable */
|
|
|
+ if (!chip->ops->position_check ||
|
|
|
+ chip->ops->position_check(chip, azx_dev)) {
|
|
|
+ spin_unlock(&chip->reg_lock);
|
|
|
+ snd_pcm_period_elapsed(azx_dev->core.substream);
|
|
|
+ spin_lock(&chip->reg_lock);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
irqreturn_t azx_interrupt(int irq, void *dev_id)
|
|
|
{
|
|
|
struct azx *chip = dev_id;
|
|
|
- struct azx_dev *azx_dev;
|
|
|
+ struct hdac_bus *bus = azx_bus(chip);
|
|
|
u32 status;
|
|
|
- u8 sd_status;
|
|
|
- int i;
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
if (azx_has_pm_runtime(chip))
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@@ -1723,23 +1638,7 @@ irqreturn_t azx_interrupt(int irq, void *dev_id)
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return IRQ_NONE;
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}
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- for (i = 0; i < chip->num_streams; i++) {
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- azx_dev = &chip->azx_dev[i];
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- if (status & azx_dev->sd_int_sta_mask) {
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- sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
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- azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
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- if (!azx_dev->substream || !azx_dev->running ||
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- !(sd_status & SD_INT_COMPLETE))
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- continue;
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- /* check whether this IRQ is really acceptable */
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- if (!chip->ops->position_check ||
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- chip->ops->position_check(chip, azx_dev)) {
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- spin_unlock(&chip->reg_lock);
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- snd_pcm_period_elapsed(azx_dev->substream);
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- spin_lock(&chip->reg_lock);
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- }
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- }
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- }
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+ snd_hdac_bus_handle_stream_irq(bus, status, stream_update);
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/* clear rirb int */
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status = azx_readb(chip, RIRBSTS);
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@@ -1769,7 +1668,7 @@ static int probe_codec(struct azx *chip, int addr)
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{
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unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
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(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
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- struct hdac_bus *bus = &chip->bus->core;
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+ struct hdac_bus *bus = azx_bus(chip);
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int err;
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unsigned int res;
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@@ -1927,33 +1826,32 @@ int azx_codec_configure(struct azx *chip)
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}
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EXPORT_SYMBOL_GPL(azx_codec_configure);
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-
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-static bool is_input_stream(struct azx *chip, unsigned char index)
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+static int stream_direction(struct azx *chip, unsigned char index)
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{
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- return (index >= chip->capture_index_offset &&
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- index < chip->capture_index_offset + chip->capture_streams);
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+ if (index >= chip->capture_index_offset &&
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+ index < chip->capture_index_offset + chip->capture_streams)
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+ return SNDRV_PCM_STREAM_CAPTURE;
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+ return SNDRV_PCM_STREAM_PLAYBACK;
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}
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/* initialize SD streams */
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int azx_init_stream(struct azx *chip)
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{
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int i;
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- int in_stream_tag = 0;
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- int out_stream_tag = 0;
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+ int stream_tags[2] = { 0, 0 };
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/* initialize each stream (aka device)
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* assign the starting bdl address to each stream (device)
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* and initialize
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*/
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for (i = 0; i < chip->num_streams; i++) {
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- struct azx_dev *azx_dev = &chip->azx_dev[i];
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- azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
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- /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
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- azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
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- /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
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- azx_dev->sd_int_sta_mask = 1 << i;
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- azx_dev->index = i;
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+ struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
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+ int dir, tag;
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+
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+ if (!azx_dev)
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+ return -ENOMEM;
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+ dir = stream_direction(chip, i);
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/* stream tag must be unique throughout
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* the stream direction group,
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* valid values 1...15
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@@ -1961,12 +1859,11 @@ int azx_init_stream(struct azx *chip)
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* AZX_DCAPS_SEPARATE_STREAM_TAG is used
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*/
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if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
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- azx_dev->stream_tag =
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- is_input_stream(chip, i) ?
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- ++in_stream_tag :
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- ++out_stream_tag;
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+ tag = ++stream_tags[dir];
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else
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- azx_dev->stream_tag = i + 1;
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+ tag = i + 1;
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+ snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
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+ i, dir, tag);
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}
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return 0;
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