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@@ -2610,12 +2610,6 @@ static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
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}
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/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
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-static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
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- int entry)
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-{
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- return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
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-}
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-
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static u32 sh_eth_tsu_get_post_mask(int entry)
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{
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return 0x0f << (28 - ((entry % 8) * 4));
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@@ -2630,27 +2624,25 @@ static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
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int entry)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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+ int reg = TSU_POST1 + entry / 8;
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u32 tmp;
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- void *reg_offset;
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- reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
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- tmp = ioread32(reg_offset);
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- iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
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+ tmp = sh_eth_tsu_read(mdp, reg);
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+ sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
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}
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static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
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int entry)
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{
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struct sh_eth_private *mdp = netdev_priv(ndev);
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+ int reg = TSU_POST1 + entry / 8;
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u32 post_mask, ref_mask, tmp;
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- void *reg_offset;
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- reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
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post_mask = sh_eth_tsu_get_post_mask(entry);
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ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
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- tmp = ioread32(reg_offset);
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- iowrite32(tmp & ~post_mask, reg_offset);
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+ tmp = sh_eth_tsu_read(mdp, reg);
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+ sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
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/* If other port enables, the function returns "true" */
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return tmp & ref_mask;
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