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@@ -38,6 +38,10 @@ static const uint32_t virtio_gpu_formats[] = {
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DRM_FORMAT_ABGR8888,
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DRM_FORMAT_ABGR8888,
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};
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};
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+static const uint32_t virtio_gpu_cursor_formats[] = {
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+ DRM_FORMAT_ARGB8888,
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+};
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+
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static void virtio_gpu_plane_destroy(struct drm_plane *plane)
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static void virtio_gpu_plane_destroy(struct drm_plane *plane)
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{
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{
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kfree(plane);
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kfree(plane);
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@@ -58,8 +62,8 @@ static int virtio_gpu_plane_atomic_check(struct drm_plane *plane,
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return 0;
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return 0;
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}
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}
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-static void virtio_gpu_plane_atomic_update(struct drm_plane *plane,
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- struct drm_plane_state *old_state)
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+static void virtio_gpu_primary_plane_update(struct drm_plane *plane,
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+ struct drm_plane_state *old_state)
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{
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{
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struct drm_device *dev = plane->dev;
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struct drm_device *dev = plane->dev;
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struct virtio_gpu_device *vgdev = dev->dev_private;
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struct virtio_gpu_device *vgdev = dev->dev_private;
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@@ -81,55 +85,149 @@ static void virtio_gpu_plane_atomic_update(struct drm_plane *plane,
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if (bo->dumb) {
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if (bo->dumb) {
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virtio_gpu_cmd_transfer_to_host_2d
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virtio_gpu_cmd_transfer_to_host_2d
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(vgdev, handle, 0,
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(vgdev, handle, 0,
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- cpu_to_le32(plane->state->crtc_w),
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- cpu_to_le32(plane->state->crtc_h),
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- plane->state->crtc_x, plane->state->crtc_y, NULL);
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+ cpu_to_le32(plane->state->src_w >> 16),
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+ cpu_to_le32(plane->state->src_h >> 16),
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+ plane->state->src_x >> 16,
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+ plane->state->src_y >> 16, NULL);
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}
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}
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} else {
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} else {
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handle = 0;
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handle = 0;
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}
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}
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- DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d\n", handle,
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+ DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n", handle,
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plane->state->crtc_w, plane->state->crtc_h,
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plane->state->crtc_w, plane->state->crtc_h,
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- plane->state->crtc_x, plane->state->crtc_y);
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+ plane->state->crtc_x, plane->state->crtc_y,
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+ plane->state->src_w >> 16,
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+ plane->state->src_h >> 16,
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+ plane->state->src_x >> 16,
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+ plane->state->src_y >> 16);
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virtio_gpu_cmd_set_scanout(vgdev, output->index, handle,
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virtio_gpu_cmd_set_scanout(vgdev, output->index, handle,
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- plane->state->crtc_w,
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- plane->state->crtc_h,
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- plane->state->crtc_x,
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- plane->state->crtc_y);
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+ plane->state->src_w >> 16,
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+ plane->state->src_h >> 16,
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+ plane->state->src_x >> 16,
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+ plane->state->src_y >> 16);
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virtio_gpu_cmd_resource_flush(vgdev, handle,
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virtio_gpu_cmd_resource_flush(vgdev, handle,
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- plane->state->crtc_x,
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- plane->state->crtc_y,
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- plane->state->crtc_w,
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- plane->state->crtc_h);
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+ plane->state->src_x >> 16,
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+ plane->state->src_y >> 16,
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+ plane->state->src_w >> 16,
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+ plane->state->src_h >> 16);
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+}
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+
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+static void virtio_gpu_cursor_plane_update(struct drm_plane *plane,
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+ struct drm_plane_state *old_state)
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+{
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+ struct drm_device *dev = plane->dev;
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+ struct virtio_gpu_device *vgdev = dev->dev_private;
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+ struct virtio_gpu_output *output = NULL;
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+ struct virtio_gpu_framebuffer *vgfb;
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+ struct virtio_gpu_fence *fence = NULL;
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+ struct virtio_gpu_object *bo = NULL;
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+ uint32_t handle;
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+ int ret = 0;
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+
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+ if (plane->state->crtc)
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+ output = drm_crtc_to_virtio_gpu_output(plane->state->crtc);
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+ if (old_state->crtc)
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+ output = drm_crtc_to_virtio_gpu_output(old_state->crtc);
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+ WARN_ON(!output);
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+
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+ if (plane->state->fb) {
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+ vgfb = to_virtio_gpu_framebuffer(plane->state->fb);
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+ bo = gem_to_virtio_gpu_obj(vgfb->obj);
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+ handle = bo->hw_res_handle;
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+ } else {
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+ handle = 0;
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+ }
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+
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+ if (bo && bo->dumb && (plane->state->fb != old_state->fb)) {
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+ /* new cursor -- update & wait */
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+ virtio_gpu_cmd_transfer_to_host_2d
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+ (vgdev, handle, 0,
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+ cpu_to_le32(plane->state->crtc_w),
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+ cpu_to_le32(plane->state->crtc_h),
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+ 0, 0, &fence);
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+ ret = virtio_gpu_object_reserve(bo, false);
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+ if (!ret) {
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+ reservation_object_add_excl_fence(bo->tbo.resv,
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+ &fence->f);
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+ fence_put(&fence->f);
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+ fence = NULL;
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+ virtio_gpu_object_unreserve(bo);
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+ virtio_gpu_object_wait(bo, false);
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+ }
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+ }
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+
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+ if (plane->state->fb != old_state->fb) {
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+ DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle,
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+ plane->state->crtc_x,
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+ plane->state->crtc_y,
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+ plane->state->fb ? plane->state->fb->hot_x : 0,
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+ plane->state->fb ? plane->state->fb->hot_y : 0);
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+ output->cursor.hdr.type =
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+ cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR);
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+ output->cursor.resource_id = cpu_to_le32(handle);
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+ if (plane->state->fb) {
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+ output->cursor.hot_x =
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+ cpu_to_le32(plane->state->fb->hot_x);
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+ output->cursor.hot_y =
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+ cpu_to_le32(plane->state->fb->hot_y);
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+ } else {
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+ output->cursor.hot_x = cpu_to_le32(0);
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+ output->cursor.hot_y = cpu_to_le32(0);
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+ }
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+ } else {
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+ DRM_DEBUG("move +%d+%d\n",
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+ plane->state->crtc_x,
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+ plane->state->crtc_y);
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+ output->cursor.hdr.type =
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+ cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR);
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+ }
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+ output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x);
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+ output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y);
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+ virtio_gpu_cursor_ping(vgdev, output);
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}
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}
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+static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = {
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+ .atomic_check = virtio_gpu_plane_atomic_check,
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+ .atomic_update = virtio_gpu_primary_plane_update,
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+};
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-static const struct drm_plane_helper_funcs virtio_gpu_plane_helper_funcs = {
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+static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = {
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.atomic_check = virtio_gpu_plane_atomic_check,
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.atomic_check = virtio_gpu_plane_atomic_check,
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- .atomic_update = virtio_gpu_plane_atomic_update,
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+ .atomic_update = virtio_gpu_cursor_plane_update,
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};
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};
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struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
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struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
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+ enum drm_plane_type type,
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int index)
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int index)
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{
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{
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struct drm_device *dev = vgdev->ddev;
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struct drm_device *dev = vgdev->ddev;
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+ const struct drm_plane_helper_funcs *funcs;
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struct drm_plane *plane;
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struct drm_plane *plane;
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- int ret;
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+ const uint32_t *formats;
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+ int ret, nformats;
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plane = kzalloc(sizeof(*plane), GFP_KERNEL);
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plane = kzalloc(sizeof(*plane), GFP_KERNEL);
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if (!plane)
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if (!plane)
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return ERR_PTR(-ENOMEM);
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return ERR_PTR(-ENOMEM);
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+ if (type == DRM_PLANE_TYPE_CURSOR) {
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+ formats = virtio_gpu_cursor_formats;
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+ nformats = ARRAY_SIZE(virtio_gpu_cursor_formats);
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+ funcs = &virtio_gpu_cursor_helper_funcs;
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+ } else {
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+ formats = virtio_gpu_formats;
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+ nformats = ARRAY_SIZE(virtio_gpu_formats);
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+ funcs = &virtio_gpu_primary_helper_funcs;
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+ }
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ret = drm_universal_plane_init(dev, plane, 1 << index,
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ret = drm_universal_plane_init(dev, plane, 1 << index,
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&virtio_gpu_plane_funcs,
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&virtio_gpu_plane_funcs,
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- virtio_gpu_formats,
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- ARRAY_SIZE(virtio_gpu_formats),
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- DRM_PLANE_TYPE_PRIMARY, NULL);
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+ formats, nformats,
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+ type, NULL);
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if (ret)
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if (ret)
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goto err_plane_init;
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goto err_plane_init;
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- drm_plane_helper_add(plane, &virtio_gpu_plane_helper_funcs);
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+ drm_plane_helper_add(plane, funcs);
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return plane;
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return plane;
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err_plane_init:
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err_plane_init:
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