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@@ -38,7 +38,6 @@ struct pcie_soc_ops {
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struct hisi_pcie {
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struct regmap *subctrl;
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- void __iomem *reg_base;
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u32 port_id;
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struct pcie_port pp;
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struct pcie_soc_ops *soc_ops;
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@@ -47,12 +46,12 @@ struct hisi_pcie {
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static inline void hisi_pcie_apb_writel(struct hisi_pcie *hisi_pcie,
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u32 val, u32 reg)
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{
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- writel(val, hisi_pcie->reg_base + reg);
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+ writel(val, hisi_pcie->pp.dbi_base + reg);
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}
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static inline u32 hisi_pcie_apb_readl(struct hisi_pcie *hisi_pcie, u32 reg)
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{
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- return readl(hisi_pcie->reg_base + reg);
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+ return readl(hisi_pcie->pp.dbi_base + reg);
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}
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/* HipXX PCIe host only supports 32-bit config access */
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@@ -198,14 +197,12 @@ static int hisi_pcie_probe(struct platform_device *pdev)
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}
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reg = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbi");
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- hisi_pcie->reg_base = devm_ioremap_resource(dev, reg);
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- if (IS_ERR(hisi_pcie->reg_base)) {
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+ pp->dbi_base = devm_ioremap_resource(dev, reg);
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+ if (IS_ERR(pp->dbi_base)) {
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dev_err(dev, "cannot get rc_dbi base\n");
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- return PTR_ERR(hisi_pcie->reg_base);
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+ return PTR_ERR(pp->dbi_base);
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}
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- hisi_pcie->pp.dbi_base = hisi_pcie->reg_base;
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-
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ret = hisi_add_pcie_port(pp, pdev);
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if (ret)
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return ret;
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