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@@ -105,7 +105,8 @@ struct nd_cmd_ars_cap {
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__u32 status;
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__u32 status;
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__u32 max_ars_out;
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__u32 max_ars_out;
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__u32 clear_err_unit;
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__u32 clear_err_unit;
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- __u32 reserved;
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+ __u16 flags;
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+ __u16 reserved;
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} __packed;
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} __packed;
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struct nd_cmd_ars_start {
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struct nd_cmd_ars_start {
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@@ -144,6 +145,43 @@ struct nd_cmd_clear_error {
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__u64 cleared;
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__u64 cleared;
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} __packed;
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} __packed;
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+struct nd_cmd_trans_spa {
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+ __u64 spa;
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+ __u32 status;
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+ __u8 flags;
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+ __u8 _reserved[3];
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+ __u64 trans_length;
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+ __u32 num_nvdimms;
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+ struct nd_nvdimm_device {
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+ __u32 nfit_device_handle;
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+ __u32 _reserved;
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+ __u64 dpa;
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+ } __packed devices[0];
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+
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+} __packed;
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+
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+struct nd_cmd_ars_err_inj {
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+ __u64 err_inj_spa_range_base;
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+ __u64 err_inj_spa_range_length;
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+ __u8 err_inj_options;
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+ __u32 status;
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+} __packed;
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+
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+struct nd_cmd_ars_err_inj_clr {
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+ __u64 err_inj_clr_spa_range_base;
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+ __u64 err_inj_clr_spa_range_length;
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+ __u32 status;
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+} __packed;
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+
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+struct nd_cmd_ars_err_inj_stat {
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+ __u32 status;
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+ __u32 inj_err_rec_count;
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+ struct nd_error_stat_query_record {
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+ __u64 err_inj_stat_spa_range_base;
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+ __u64 err_inj_stat_spa_range_length;
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+ } __packed record[0];
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+} __packed;
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+
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enum {
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enum {
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ND_CMD_IMPLEMENTED = 0,
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ND_CMD_IMPLEMENTED = 0,
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