|
@@ -485,7 +485,7 @@
|
|
#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
|
|
#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
|
|
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
|
|
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
|
|
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
|
|
#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
|
|
-#define SSB_SPROM8_TEMPDELTA 0x00BA
|
|
|
|
|
|
+#define SSB_SPROM8_TEMPDELTA 0x00BC
|
|
#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
|
|
#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
|
|
#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
|
|
#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
|
|
#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
|
|
#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
|