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@@ -102,6 +102,7 @@
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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+ dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
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clocks {
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#address-cells = <2>;
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@@ -352,6 +353,15 @@
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reg-names = "csr-reg";
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clock-output-names = "pcie4clk";
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};
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+
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+ dmaclk: dmaclk@1f27c000 {
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+ compatible = "apm,xgene-device-clock";
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+ #clock-cells = <1>;
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+ clocks = <&socplldiv2 0>;
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+ reg = <0x0 0x1f27c000 0x0 0x1000>;
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+ reg-names = "csr-reg";
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+ clock-output-names = "dmaclk";
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+ };
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};
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pcie0: pcie@1f2b0000 {
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@@ -656,5 +666,21 @@
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interrupts = <0x0 0x41 0x4>;
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clocks = <&rngpkaclk 0>;
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};
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+
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+ dma: dma@1f270000 {
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+ compatible = "apm,xgene-storm-dma";
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+ device_type = "dma";
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+ reg = <0x0 0x1f270000 0x0 0x10000>,
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+ <0x0 0x1f200000 0x0 0x10000>,
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+ <0x0 0x1b008000 0x0 0x2000>,
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+ <0x0 0x1054a000 0x0 0x100>;
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+ interrupts = <0x0 0x82 0x4>,
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+ <0x0 0xb8 0x4>,
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+ <0x0 0xb9 0x4>,
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+ <0x0 0xba 0x4>,
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+ <0x0 0xbb 0x4>;
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+ dma-coherent;
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+ clocks = <&dmaclk 0>;
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+ };
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};
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};
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