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@@ -241,6 +241,23 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
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return flags;
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}
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+static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
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+{
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+ u32 flags = 0;
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+
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+ if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
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+ u32 ctxnum, base;
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+
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+ base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
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+ ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
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+
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+ base >>= PAGE_SHIFT;
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+ flags |= (base << GUC_CTL_BASE_ADDR_SHIFT) |
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+ (ctxnum << GUC_CTL_CTXNUM_IN16_SHIFT);
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+ }
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+ return flags;
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+}
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+
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static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
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{
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u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
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@@ -282,16 +299,7 @@ void intel_guc_init_params(struct intel_guc *guc)
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params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
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params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
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params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
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-
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- /* If GuC submission is enabled, set up additional parameters here */
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- if (USES_GUC_SUBMISSION(dev_priv)) {
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- u32 pgs = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
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- u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
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-
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- pgs >>= PAGE_SHIFT;
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- params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
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- (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
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- }
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+ params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
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/*
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* All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
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