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@@ -1349,37 +1349,24 @@ static int i965_reset_complete(struct drm_device *dev)
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{
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u8 gdrst;
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pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
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- return (gdrst & GRDOM_RESET_ENABLE) == 0;
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+ return (gdrst & GRDOM_RESET_STATUS) == 0;
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}
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static int i965_do_reset(struct drm_device *dev)
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{
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- int ret;
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-
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- /* FIXME: i965g/gm need a display save/restore for gpu reset. */
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- return -ENODEV;
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-
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- /*
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- * Set the domains we want to reset (GRDOM/bits 2 and 3) as
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- * well as the reset bit (GR/bit 0). Setting the GR bit
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- * triggers the reset; when done, the hardware will clear it.
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- */
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- pci_write_config_byte(dev->pdev, I965_GDRST,
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- GRDOM_RENDER | GRDOM_RESET_ENABLE);
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- ret = wait_for(i965_reset_complete(dev), 500);
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- if (ret)
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- return ret;
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-
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- pci_write_config_byte(dev->pdev, I965_GDRST,
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- GRDOM_MEDIA | GRDOM_RESET_ENABLE);
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-
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- ret = wait_for(i965_reset_complete(dev), 500);
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- if (ret)
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- return ret;
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-
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+ /* assert reset for at least 20 usec */
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+ pci_write_config_byte(dev->pdev, I965_GDRST, GRDOM_RESET_ENABLE);
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+ udelay(20);
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pci_write_config_byte(dev->pdev, I965_GDRST, 0);
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- return 0;
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+ return wait_for(i965_reset_complete(dev), 500);
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+}
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+
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+static int g4x_reset_complete(struct drm_device *dev)
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+{
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+ u8 gdrst;
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+ pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
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+ return (gdrst & GRDOM_RESET_ENABLE) == 0;
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}
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static int g4x_do_reset(struct drm_device *dev)
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@@ -1389,7 +1376,7 @@ static int g4x_do_reset(struct drm_device *dev)
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pci_write_config_byte(dev->pdev, I965_GDRST,
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GRDOM_RENDER | GRDOM_RESET_ENABLE);
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- ret = wait_for(i965_reset_complete(dev), 500);
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+ ret = wait_for(g4x_reset_complete(dev), 500);
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if (ret)
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return ret;
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@@ -1399,7 +1386,7 @@ static int g4x_do_reset(struct drm_device *dev)
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pci_write_config_byte(dev->pdev, I965_GDRST,
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GRDOM_MEDIA | GRDOM_RESET_ENABLE);
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- ret = wait_for(i965_reset_complete(dev), 500);
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+ ret = wait_for(g4x_reset_complete(dev), 500);
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if (ret)
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return ret;
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