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@@ -45,13 +45,13 @@ Updated: Sat, 25 Jan 2003 13:24:40 -0800
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#define NI6527_DI_REG(x) (0x00 + (x))
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#define NI6527_DO_REG(x) (0x03 + (x))
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#define NI6527_ID_REG 0x06
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-
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-#define Clear_Register 0x07
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-#define ClrEdge 0x08
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-#define ClrOverflow 0x04
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-#define ClrFilter 0x02
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-#define ClrInterval 0x01
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-
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+#define NI6527_CLR_REG 0x07
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+#define NI6527_CLR_EDGE (1 << 3)
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+#define NI6527_CLR_OVERFLOW (1 << 2)
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+#define NI6527_CLR_FILT (1 << 1)
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+#define NI6527_CLR_INTERVAL (1 << 0)
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+#define NI6527_CLR_IRQS (NI6527_CLR_EDGE | NI6527_CLR_OVERFLOW)
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+#define NI6527_CLR_RESET_FILT (NI6527_CLR_FILT | NI6527_CLR_INTERVAL)
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#define NI6527_FILT_INTERVAL_REG(x) (0x08 + (x))
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#define NI6527_FILT_ENA_REG(x) (0x0c + (x))
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#define NI6527_STATUS_REG 0x14
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@@ -104,7 +104,7 @@ static void ni6527_set_filter_interval(struct comedi_device *dev,
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writeb((val >> 8) & 0xff, mmio + NI6527_FILT_INTERVAL_REG(1));
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writeb((val >> 16) & 0x0f, mmio + NI6527_FILT_INTERVAL_REG(2));
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- writeb(ClrInterval, mmio + Clear_Register);
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+ writeb(NI6527_CLR_INTERVAL, mmio + NI6527_CLR_REG);
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devpriv->filter_interval = val;
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}
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@@ -218,8 +218,7 @@ static irqreturn_t ni6527_interrupt(int irq, void *d)
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comedi_event(dev, s);
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}
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- writeb(ClrEdge | ClrOverflow,
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- mmio + Clear_Register);
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+ writeb(NI6527_CLR_IRQS, mmio + NI6527_CLR_REG);
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return IRQ_HANDLED;
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}
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@@ -272,8 +271,8 @@ static int ni6527_intr_cmd(struct comedi_device *dev,
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struct ni6527_private *devpriv = dev->private;
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/* struct comedi_cmd *cmd = &s->async->cmd; */
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- writeb(ClrEdge | ClrOverflow,
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- devpriv->mite->daq_io_addr + Clear_Register);
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+ writeb(NI6527_CLR_IRQS,
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+ devpriv->mite->daq_io_addr + NI6527_CLR_REG);
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writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
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MasterInterruptEnable | EdgeIntEnable,
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devpriv->mite->daq_io_addr + Master_Interrupt_Control);
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@@ -401,8 +400,8 @@ static int ni6527_auto_attach(struct comedi_device *dev,
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ni6527_set_filter_enable(dev, 0);
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- writeb(ClrEdge | ClrOverflow | ClrFilter | ClrInterval,
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- devpriv->mite->daq_io_addr + Clear_Register);
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+ writeb(NI6527_CLR_IRQS | NI6527_CLR_RESET_FILT,
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+ devpriv->mite->daq_io_addr + NI6527_CLR_REG);
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writeb(0x00, devpriv->mite->daq_io_addr + Master_Interrupt_Control);
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ret = request_irq(mite_irq(devpriv->mite), ni6527_interrupt,
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