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@@ -217,8 +217,30 @@
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/* divider clocks */
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/* divider clocks */
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#define CLK_DOUT_PIXEL 768
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#define CLK_DOUT_PIXEL 768
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+#define CLK_DOUT_ACLK400_WCORE 769
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+#define CLK_DOUT_ACLK400_ISP 770
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+#define CLK_DOUT_ACLK400_MSCL 771
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+#define CLK_DOUT_ACLK200 772
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+#define CLK_DOUT_ACLK200_FSYS2 773
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+#define CLK_DOUT_ACLK100_NOC 774
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+#define CLK_DOUT_PCLK200_FSYS 775
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+#define CLK_DOUT_ACLK200_FSYS 776
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+#define CLK_DOUT_ACLK333_432_GSCL 777
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+#define CLK_DOUT_ACLK333_432_ISP 778
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+#define CLK_DOUT_ACLK66 779
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+#define CLK_DOUT_ACLK333_432_ISP0 780
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+#define CLK_DOUT_ACLK266 781
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+#define CLK_DOUT_ACLK166 782
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+#define CLK_DOUT_ACLK333 783
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+#define CLK_DOUT_ACLK333_G2D 784
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+#define CLK_DOUT_ACLK266_G2D 785
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+#define CLK_DOUT_ACLK_G3D 786
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+#define CLK_DOUT_ACLK300_JPEG 787
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+#define CLK_DOUT_ACLK300_DISP1 788
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+#define CLK_DOUT_ACLK300_GSCL 789
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+#define CLK_DOUT_ACLK400_DISP1 790
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/* must be greater than maximal clock id */
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/* must be greater than maximal clock id */
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-#define CLK_NR_CLKS 769
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+#define CLK_NR_CLKS 791
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
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