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@@ -0,0 +1,719 @@
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+/*
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+ * Copyright 2014 Emilio López <emilio@elopez.com.ar>
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+ * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
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+ * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
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+ *
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+ * Based on the Allwinner SDK driver, released under the GPL.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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+#include <linux/slab.h>
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+#include <linux/of.h>
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+#include <linux/of_platform.h>
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+#include <linux/of_address.h>
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+#include <linux/clk.h>
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+#include <linux/regmap.h>
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+
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+#include <sound/core.h>
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+#include <sound/pcm.h>
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+#include <sound/pcm_params.h>
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+#include <sound/soc.h>
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+#include <sound/tlv.h>
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+#include <sound/initval.h>
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+#include <sound/dmaengine_pcm.h>
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+
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+/* Codec DAC register offsets and bit fields */
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+#define SUN4I_CODEC_DAC_DPC (0x00)
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+#define SUN4I_CODEC_DAC_DPC_EN_DA (31)
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+#define SUN4I_CODEC_DAC_DPC_DVOL (12)
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+#define SUN4I_CODEC_DAC_FIFOC (0x04)
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+#define SUN4I_CODEC_DAC_FIFOC_DAC_FS (29)
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+#define SUN4I_CODEC_DAC_FIFOC_FIR_VERSION (28)
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+#define SUN4I_CODEC_DAC_FIFOC_SEND_LASAT (26)
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+#define SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE (24)
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+#define SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT (21)
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+#define SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL (8)
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+#define SUN4I_CODEC_DAC_FIFOC_MONO_EN (6)
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+#define SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS (5)
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+#define SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN (4)
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+#define SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH (0)
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+#define SUN4I_CODEC_DAC_FIFOS (0x08)
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+#define SUN4I_CODEC_DAC_TXDATA (0x0c)
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+#define SUN4I_CODEC_DAC_ACTL (0x10)
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+#define SUN4I_CODEC_DAC_ACTL_DACAENR (31)
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+#define SUN4I_CODEC_DAC_ACTL_DACAENL (30)
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+#define SUN4I_CODEC_DAC_ACTL_MIXEN (29)
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+#define SUN4I_CODEC_DAC_ACTL_LDACLMIXS (15)
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+#define SUN4I_CODEC_DAC_ACTL_RDACRMIXS (14)
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+#define SUN4I_CODEC_DAC_ACTL_LDACRMIXS (13)
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+#define SUN4I_CODEC_DAC_ACTL_DACPAS (8)
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+#define SUN4I_CODEC_DAC_ACTL_MIXPAS (7)
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+#define SUN4I_CODEC_DAC_ACTL_PA_MUTE (6)
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+#define SUN4I_CODEC_DAC_ACTL_PA_VOL (0)
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+#define SUN4I_CODEC_DAC_TUNE (0x14)
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+#define SUN4I_CODEC_DAC_DEBUG (0x18)
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+
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+/* Codec ADC register offsets and bit fields */
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+#define SUN4I_CODEC_ADC_FIFOC (0x1c)
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+#define SUN4I_CODEC_ADC_FIFOC_EN_AD (28)
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+#define SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE (24)
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+#define SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (8)
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+#define SUN4I_CODEC_ADC_FIFOC_MONO_EN (7)
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+#define SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (6)
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+#define SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN (4)
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+#define SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH (0)
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+#define SUN4I_CODEC_ADC_FIFOS (0x20)
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+#define SUN4I_CODEC_ADC_RXDATA (0x24)
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+#define SUN4I_CODEC_ADC_ACTL (0x28)
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+#define SUN4I_CODEC_ADC_ACTL_ADC_R_EN (31)
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+#define SUN4I_CODEC_ADC_ACTL_ADC_L_EN (30)
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+#define SUN4I_CODEC_ADC_ACTL_PREG1EN (29)
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+#define SUN4I_CODEC_ADC_ACTL_PREG2EN (28)
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+#define SUN4I_CODEC_ADC_ACTL_VMICEN (27)
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+#define SUN4I_CODEC_ADC_ACTL_VADCG (20)
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+#define SUN4I_CODEC_ADC_ACTL_ADCIS (17)
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+#define SUN4I_CODEC_ADC_ACTL_PA_EN (4)
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+#define SUN4I_CODEC_ADC_ACTL_DDE (3)
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+#define SUN4I_CODEC_ADC_DEBUG (0x2c)
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+
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+/* Other various ADC registers */
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+#define SUN4I_CODEC_DAC_TXCNT (0x30)
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+#define SUN4I_CODEC_ADC_RXCNT (0x34)
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+#define SUN4I_CODEC_AC_SYS_VERI (0x38)
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+#define SUN4I_CODEC_AC_MIC_PHONE_CAL (0x3c)
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+
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+struct sun4i_codec {
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+ struct device *dev;
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+ struct regmap *regmap;
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+ struct clk *clk_apb;
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+ struct clk *clk_module;
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+
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+ struct snd_dmaengine_dai_dma_data playback_dma_data;
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+};
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+
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+static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
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+{
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+ /*
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+ * FIXME: according to the BSP, we might need to drive a PA
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+ * GPIO high here on some boards
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+ */
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+
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+ /* Flush TX FIFO */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH),
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+ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
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+
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+ /* Enable DAC DRQ */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
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+ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
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+}
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+
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+static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
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+{
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+ /*
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+ * FIXME: according to the BSP, we might need to drive a PA
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+ * GPIO low here on some boards
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+ */
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+
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+ /* Disable DAC DRQ */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
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+ 0);
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+}
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+
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+static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
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+ struct snd_soc_dai *dai)
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+{
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+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
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+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
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+
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+ if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
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+ return -ENOTSUPP;
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+
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+ switch (cmd) {
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+ case SNDRV_PCM_TRIGGER_START:
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+ case SNDRV_PCM_TRIGGER_RESUME:
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+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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+ sun4i_codec_start_playback(scodec);
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+ break;
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+
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+ case SNDRV_PCM_TRIGGER_STOP:
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+ case SNDRV_PCM_TRIGGER_SUSPEND:
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+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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+ sun4i_codec_stop_playback(scodec);
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+ break;
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+
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static int sun4i_codec_prepare(struct snd_pcm_substream *substream,
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+ struct snd_soc_dai *dai)
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+{
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+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
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+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
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+ u32 val;
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+
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+ if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
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+ return -ENOTSUPP;
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+
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+ /* Flush the TX FIFO */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH),
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+ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
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+
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+ /* Set TX FIFO Empty Trigger Level */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
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+ 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
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+
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+ if (substream->runtime->rate > 32000)
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+ /* Use 64 bits FIR filter */
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+ val = 0;
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+ else
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+ /* Use 32 bits FIR filter */
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+ val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
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+
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
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+ val);
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+
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+ /* Send zeros when we have an underrun */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT),
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+ 0);
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+
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+ return 0;
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+}
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+
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+static unsigned long sun4i_codec_get_mod_freq(struct snd_pcm_hw_params *params)
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+{
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+ unsigned int rate = params_rate(params);
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+
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+ switch (rate) {
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+ case 176400:
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+ case 88200:
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+ case 44100:
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+ case 33075:
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+ case 22050:
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+ case 14700:
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+ case 11025:
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+ case 7350:
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+ return 22579200;
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+
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+ case 192000:
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+ case 96000:
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+ case 48000:
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+ case 32000:
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+ case 24000:
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+ case 16000:
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+ case 12000:
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+ case 8000:
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+ return 24576000;
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+
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+ default:
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+ return 0;
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+ }
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+}
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+
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+static int sun4i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
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+{
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+ unsigned int rate = params_rate(params);
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+
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+ switch (rate) {
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+ case 192000:
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+ case 176400:
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+ return 6;
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+
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+ case 96000:
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+ case 88200:
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+ return 7;
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+
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+ case 48000:
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+ case 44100:
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+ return 0;
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+
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+ case 32000:
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+ case 33075:
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+ return 1;
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+
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+ case 24000:
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+ case 22050:
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+ return 2;
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+
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+ case 16000:
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+ case 14700:
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+ return 3;
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+
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+ case 12000:
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+ case 11025:
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+ return 4;
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+
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+ case 8000:
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+ case 7350:
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+ return 5;
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+
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+ default:
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+ return -EINVAL;
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+ }
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+}
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+
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+static int sun4i_codec_hw_params(struct snd_pcm_substream *substream,
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+ struct snd_pcm_hw_params *params,
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+ struct snd_soc_dai *dai)
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+{
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+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
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+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
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+ unsigned long clk_freq;
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+ int hwrate;
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+ u32 val;
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+
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+ if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
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+ return -ENOTSUPP;
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+
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+ clk_freq = sun4i_codec_get_mod_freq(params);
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+ if (!clk_freq)
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+ return -EINVAL;
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+
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+ if (clk_set_rate(scodec->clk_module, clk_freq))
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+ return -EINVAL;
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+
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+ hwrate = sun4i_codec_get_hw_rate(params);
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+ if (hwrate < 0)
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+ return hwrate;
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+
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+ /* Set DAC sample rate */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
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+ hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
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+
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+ /* Set the number of channels we want to use */
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+ if (params_channels(params) == 1)
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+ val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN);
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+ else
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+ val = 0;
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+
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
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+ val);
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+
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+ /* Set the number of sample bits to either 16 or 24 bits */
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+ if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS),
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+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
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+
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+ /* Set TX FIFO mode to padding the LSBs with 0 */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE),
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+ 0);
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+
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+ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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+ } else {
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS),
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+ 0);
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+
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+ /* Set TX FIFO mode to repeat the MSB */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE),
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+ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
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+
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+ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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+ }
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+
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+ return 0;
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+}
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+
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+static int sun4i_codec_startup(struct snd_pcm_substream *substream,
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+ struct snd_soc_dai *dai)
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+{
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+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
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+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
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+
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+ /*
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+ * Stop issuing DRQ when we have room for less than 16 samples
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+ * in our TX FIFO
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+ */
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+ regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
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+ 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT,
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+ 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
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+
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+ return clk_prepare_enable(scodec->clk_module);
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+}
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+
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+static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
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+ struct snd_soc_dai *dai)
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+{
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+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
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|
|
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
|
|
|
+
|
|
|
+ clk_disable_unprepare(scodec->clk_module);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
|
|
|
+ .startup = sun4i_codec_startup,
|
|
|
+ .shutdown = sun4i_codec_shutdown,
|
|
|
+ .trigger = sun4i_codec_trigger,
|
|
|
+ .hw_params = sun4i_codec_hw_params,
|
|
|
+ .prepare = sun4i_codec_prepare,
|
|
|
+};
|
|
|
+
|
|
|
+static struct snd_soc_dai_driver sun4i_codec_dai = {
|
|
|
+ .name = "Codec",
|
|
|
+ .ops = &sun4i_codec_dai_ops,
|
|
|
+ .playback = {
|
|
|
+ .stream_name = "Codec Playback",
|
|
|
+ .channels_min = 1,
|
|
|
+ .channels_max = 2,
|
|
|
+ .rate_min = 8000,
|
|
|
+ .rate_max = 192000,
|
|
|
+ .rates = SNDRV_PCM_RATE_8000_48000 |
|
|
|
+ SNDRV_PCM_RATE_96000 |
|
|
|
+ SNDRV_PCM_RATE_192000 |
|
|
|
+ SNDRV_PCM_RATE_KNOT,
|
|
|
+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
|
|
|
+ SNDRV_PCM_FMTBIT_S32_LE,
|
|
|
+ .sig_bits = 24,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/*** Codec ***/
|
|
|
+static const struct snd_kcontrol_new sun4i_codec_pa_mute =
|
|
|
+ SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
|
|
|
+
|
|
|
+static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1);
|
|
|
+
|
|
|
+static const struct snd_kcontrol_new sun4i_codec_widgets[] = {
|
|
|
+ SOC_SINGLE_TLV("PA Volume", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
|
|
|
+ sun4i_codec_pa_volume_scale),
|
|
|
+};
|
|
|
+
|
|
|
+static const struct snd_kcontrol_new sun4i_codec_left_mixer_controls[] = {
|
|
|
+ SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_LDACLMIXS, 1, 0),
|
|
|
+};
|
|
|
+
|
|
|
+static const struct snd_kcontrol_new sun4i_codec_right_mixer_controls[] = {
|
|
|
+ SOC_DAPM_SINGLE("Right DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_RDACRMIXS, 1, 0),
|
|
|
+ SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_LDACRMIXS, 1, 0),
|
|
|
+};
|
|
|
+
|
|
|
+static const struct snd_kcontrol_new sun4i_codec_pa_mixer_controls[] = {
|
|
|
+ SOC_DAPM_SINGLE("DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_DACPAS, 1, 0),
|
|
|
+ SOC_DAPM_SINGLE("Mixer Playback Switch", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_MIXPAS, 1, 0),
|
|
|
+};
|
|
|
+
|
|
|
+static const struct snd_soc_dapm_widget sun4i_codec_dapm_widgets[] = {
|
|
|
+ /* Digital parts of the DACs */
|
|
|
+ SND_SOC_DAPM_SUPPLY("DAC", SUN4I_CODEC_DAC_DPC,
|
|
|
+ SUN4I_CODEC_DAC_DPC_EN_DA, 0,
|
|
|
+ NULL, 0),
|
|
|
+
|
|
|
+ /* Analog parts of the DACs */
|
|
|
+ SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_DACAENL, 0),
|
|
|
+ SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_DACAENR, 0),
|
|
|
+
|
|
|
+ /* Mixers */
|
|
|
+ SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
|
|
|
+ sun4i_codec_left_mixer_controls,
|
|
|
+ ARRAY_SIZE(sun4i_codec_left_mixer_controls)),
|
|
|
+ SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
|
|
|
+ sun4i_codec_right_mixer_controls,
|
|
|
+ ARRAY_SIZE(sun4i_codec_right_mixer_controls)),
|
|
|
+
|
|
|
+ /* Global Mixer Enable */
|
|
|
+ SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL,
|
|
|
+ SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0),
|
|
|
+
|
|
|
+ /* Pre-Amplifier */
|
|
|
+ SND_SOC_DAPM_MIXER("Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
|
|
|
+ SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
|
|
|
+ sun4i_codec_pa_mixer_controls,
|
|
|
+ ARRAY_SIZE(sun4i_codec_pa_mixer_controls)),
|
|
|
+ SND_SOC_DAPM_SWITCH("Pre-Amplifier Mute", SND_SOC_NOPM, 0, 0,
|
|
|
+ &sun4i_codec_pa_mute),
|
|
|
+
|
|
|
+ SND_SOC_DAPM_OUTPUT("HP Right"),
|
|
|
+ SND_SOC_DAPM_OUTPUT("HP Left"),
|
|
|
+};
|
|
|
+
|
|
|
+static const struct snd_soc_dapm_route sun4i_codec_dapm_routes[] = {
|
|
|
+ /* Left DAC Routes */
|
|
|
+ { "Left DAC", NULL, "DAC" },
|
|
|
+
|
|
|
+ /* Right DAC Routes */
|
|
|
+ { "Right DAC", NULL, "DAC" },
|
|
|
+
|
|
|
+ /* Right Mixer Routes */
|
|
|
+ { "Right Mixer", NULL, "Mixer Enable" },
|
|
|
+ { "Right Mixer", "Left DAC Playback Switch", "Left DAC" },
|
|
|
+ { "Right Mixer", "Right DAC Playback Switch", "Right DAC" },
|
|
|
+
|
|
|
+ /* Left Mixer Routes */
|
|
|
+ { "Left Mixer", NULL, "Mixer Enable" },
|
|
|
+ { "Left Mixer", "Left DAC Playback Switch", "Left DAC" },
|
|
|
+
|
|
|
+ /* Pre-Amplifier Mixer Routes */
|
|
|
+ { "Pre-Amplifier", "Mixer Playback Switch", "Left Mixer" },
|
|
|
+ { "Pre-Amplifier", "Mixer Playback Switch", "Right Mixer" },
|
|
|
+ { "Pre-Amplifier", "DAC Playback Switch", "Left DAC" },
|
|
|
+ { "Pre-Amplifier", "DAC Playback Switch", "Right DAC" },
|
|
|
+
|
|
|
+ /* PA -> HP path */
|
|
|
+ { "Pre-Amplifier Mute", "Switch", "Pre-Amplifier" },
|
|
|
+ { "HP Right", NULL, "Pre-Amplifier Mute" },
|
|
|
+ { "HP Left", NULL, "Pre-Amplifier Mute" },
|
|
|
+};
|
|
|
+
|
|
|
+static struct snd_soc_codec_driver sun4i_codec_codec = {
|
|
|
+ .controls = sun4i_codec_widgets,
|
|
|
+ .num_controls = ARRAY_SIZE(sun4i_codec_widgets),
|
|
|
+ .dapm_widgets = sun4i_codec_dapm_widgets,
|
|
|
+ .num_dapm_widgets = ARRAY_SIZE(sun4i_codec_dapm_widgets),
|
|
|
+ .dapm_routes = sun4i_codec_dapm_routes,
|
|
|
+ .num_dapm_routes = ARRAY_SIZE(sun4i_codec_dapm_routes),
|
|
|
+};
|
|
|
+
|
|
|
+static const struct snd_soc_component_driver sun4i_codec_component = {
|
|
|
+ .name = "sun4i-codec",
|
|
|
+};
|
|
|
+
|
|
|
+#define SUN4I_CODEC_RATES SNDRV_PCM_RATE_8000_192000
|
|
|
+#define SUN4I_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
|
|
|
+ SNDRV_PCM_FMTBIT_S32_LE)
|
|
|
+
|
|
|
+static int sun4i_codec_dai_probe(struct snd_soc_dai *dai)
|
|
|
+{
|
|
|
+ struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
|
|
|
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
|
|
|
+
|
|
|
+ snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data,
|
|
|
+ NULL);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct snd_soc_dai_driver dummy_cpu_dai = {
|
|
|
+ .name = "sun4i-codec-cpu-dai",
|
|
|
+ .probe = sun4i_codec_dai_probe,
|
|
|
+ .playback = {
|
|
|
+ .stream_name = "Playback",
|
|
|
+ .channels_min = 1,
|
|
|
+ .channels_max = 2,
|
|
|
+ .rates = SUN4I_CODEC_RATES,
|
|
|
+ .formats = SUN4I_CODEC_FORMATS,
|
|
|
+ .sig_bits = 24,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static const struct regmap_config sun4i_codec_regmap_config = {
|
|
|
+ .reg_bits = 32,
|
|
|
+ .reg_stride = 4,
|
|
|
+ .val_bits = 32,
|
|
|
+ .max_register = SUN4I_CODEC_AC_MIC_PHONE_CAL,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct of_device_id sun4i_codec_of_match[] = {
|
|
|
+ { .compatible = "allwinner,sun4i-a10-codec" },
|
|
|
+ { .compatible = "allwinner,sun7i-a20-codec" },
|
|
|
+ {}
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
|
|
|
+
|
|
|
+static struct snd_soc_dai_link *sun4i_codec_create_link(struct device *dev,
|
|
|
+ int *num_links)
|
|
|
+{
|
|
|
+ struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link),
|
|
|
+ GFP_KERNEL);
|
|
|
+ if (!link)
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+ link->name = "cdc";
|
|
|
+ link->stream_name = "CDC PCM";
|
|
|
+ link->codec_dai_name = "Codec";
|
|
|
+ link->cpu_dai_name = dev_name(dev);
|
|
|
+ link->codec_name = dev_name(dev);
|
|
|
+ link->platform_name = dev_name(dev);
|
|
|
+ link->dai_fmt = SND_SOC_DAIFMT_I2S;
|
|
|
+
|
|
|
+ *num_links = 1;
|
|
|
+
|
|
|
+ return link;
|
|
|
+};
|
|
|
+
|
|
|
+static struct snd_soc_card *sun4i_codec_create_card(struct device *dev)
|
|
|
+{
|
|
|
+ struct snd_soc_card *card;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
|
|
|
+ if (!card)
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
|
|
|
+ if (!card->dai_link)
|
|
|
+ return NULL;
|
|
|
+
|
|
|
+ card->dev = dev;
|
|
|
+ card->name = "sun4i-codec";
|
|
|
+
|
|
|
+ ret = snd_soc_of_parse_audio_routing(card, "routing");
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "Failed to create our audio routing\n");
|
|
|
+ return NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ return card;
|
|
|
+};
|
|
|
+
|
|
|
+static int sun4i_codec_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct snd_soc_card *card;
|
|
|
+ struct sun4i_codec *scodec;
|
|
|
+ struct resource *res;
|
|
|
+ void __iomem *base;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
|
|
|
+ if (!scodec)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ scodec->dev = &pdev->dev;
|
|
|
+
|
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
+ base = devm_ioremap_resource(&pdev->dev, res);
|
|
|
+ if (IS_ERR(base)) {
|
|
|
+ dev_err(&pdev->dev, "Failed to map the registers\n");
|
|
|
+ return PTR_ERR(base);
|
|
|
+ }
|
|
|
+
|
|
|
+ scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
|
|
|
+ &sun4i_codec_regmap_config);
|
|
|
+ if (IS_ERR(scodec->regmap)) {
|
|
|
+ dev_err(&pdev->dev, "Failed to create our regmap\n");
|
|
|
+ return PTR_ERR(scodec->regmap);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Get the clocks from the DT */
|
|
|
+ scodec->clk_apb = devm_clk_get(&pdev->dev, "apb");
|
|
|
+ if (IS_ERR(scodec->clk_apb)) {
|
|
|
+ dev_err(&pdev->dev, "Failed to get the APB clock\n");
|
|
|
+ return PTR_ERR(scodec->clk_apb);
|
|
|
+ }
|
|
|
+
|
|
|
+ scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
|
|
|
+ if (IS_ERR(scodec->clk_module)) {
|
|
|
+ dev_err(&pdev->dev, "Failed to get the module clock\n");
|
|
|
+ return PTR_ERR(scodec->clk_module);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Enable the bus clock */
|
|
|
+ if (clk_prepare_enable(scodec->clk_apb)) {
|
|
|
+ dev_err(&pdev->dev, "Failed to enable the APB clock\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* DMA configuration for TX FIFO */
|
|
|
+ scodec->playback_dma_data.addr = res->start + SUN4I_CODEC_DAC_TXDATA;
|
|
|
+ scodec->playback_dma_data.maxburst = 4;
|
|
|
+ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
|
|
|
+
|
|
|
+ ret = snd_soc_register_codec(&pdev->dev, &sun4i_codec_codec,
|
|
|
+ &sun4i_codec_dai, 1);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&pdev->dev, "Failed to register our codec\n");
|
|
|
+ goto err_clk_disable;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = devm_snd_soc_register_component(&pdev->dev,
|
|
|
+ &sun4i_codec_component,
|
|
|
+ &dummy_cpu_dai, 1);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&pdev->dev, "Failed to register our DAI\n");
|
|
|
+ goto err_unregister_codec;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&pdev->dev, "Failed to register against DMAEngine\n");
|
|
|
+ goto err_unregister_codec;
|
|
|
+ }
|
|
|
+
|
|
|
+ card = sun4i_codec_create_card(&pdev->dev);
|
|
|
+ if (!card) {
|
|
|
+ dev_err(&pdev->dev, "Failed to create our card\n");
|
|
|
+ goto err_unregister_codec;
|
|
|
+ }
|
|
|
+
|
|
|
+ platform_set_drvdata(pdev, card);
|
|
|
+ snd_soc_card_set_drvdata(card, scodec);
|
|
|
+
|
|
|
+ ret = snd_soc_register_card(card);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(&pdev->dev, "Failed to register our card\n");
|
|
|
+ goto err_unregister_codec;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+err_unregister_codec:
|
|
|
+ snd_soc_unregister_codec(&pdev->dev);
|
|
|
+err_clk_disable:
|
|
|
+ clk_disable_unprepare(scodec->clk_apb);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int sun4i_codec_remove(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct snd_soc_card *card = platform_get_drvdata(pdev);
|
|
|
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
|
|
|
+
|
|
|
+ snd_soc_unregister_card(card);
|
|
|
+ snd_soc_unregister_codec(&pdev->dev);
|
|
|
+ clk_disable_unprepare(scodec->clk_apb);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct platform_driver sun4i_codec_driver = {
|
|
|
+ .driver = {
|
|
|
+ .name = "sun4i-codec",
|
|
|
+ .of_match_table = sun4i_codec_of_match,
|
|
|
+ },
|
|
|
+ .probe = sun4i_codec_probe,
|
|
|
+ .remove = sun4i_codec_remove,
|
|
|
+};
|
|
|
+module_platform_driver(sun4i_codec_driver);
|
|
|
+
|
|
|
+MODULE_DESCRIPTION("Allwinner A10 codec driver");
|
|
|
+MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
|
|
|
+MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
|
|
|
+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
|
|
|
+MODULE_LICENSE("GPL");
|
Mark Brown
10 jaren geleden