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@@ -57,8 +57,8 @@
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#include <linux/of_address.h>
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#include <linux/debugfs.h>
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#include <linux/log2.h>
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-#include <linux/syscore_ops.h>
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#include <linux/memblock.h>
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+#include <linux/syscore_ops.h>
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/*
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* DDR target is the same on all platforms.
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@@ -70,6 +70,7 @@
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*/
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#define WIN_CTRL_OFF 0x0000
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#define WIN_CTRL_ENABLE BIT(0)
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+/* Only on HW I/O coherency capable platforms */
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#define WIN_CTRL_SYNCBARRIER BIT(1)
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#define WIN_CTRL_TGT_MASK 0xf0
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#define WIN_CTRL_TGT_SHIFT 4
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@@ -102,9 +103,7 @@
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/* Relative to mbusbridge_base */
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#define MBUS_BRIDGE_CTRL_OFF 0x0
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-#define MBUS_BRIDGE_SIZE_MASK 0xffff0000
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#define MBUS_BRIDGE_BASE_OFF 0x4
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-#define MBUS_BRIDGE_BASE_MASK 0xffff0000
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/* Maximum number of windows, for all known platforms */
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#define MBUS_WINS_MAX 20
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@@ -154,13 +153,39 @@ struct mvebu_mbus_state {
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static struct mvebu_mbus_state mbus_state;
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+/*
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+ * We provide two variants of the mv_mbus_dram_info() function:
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+ *
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+ * - The normal one, where the described DRAM ranges may overlap with
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+ * the I/O windows, but for which the DRAM ranges are guaranteed to
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+ * have a power of two size. Such ranges are suitable for the DMA
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+ * masters that only DMA between the RAM and the device, which is
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+ * actually all devices except the crypto engines.
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+ *
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+ * - The 'nooverlap' one, where the described DRAM ranges are
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+ * guaranteed to not overlap with the I/O windows, but for which the
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+ * DRAM ranges will not have power of two sizes. They will only be
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+ * aligned on a 64 KB boundary, and have a size multiple of 64
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+ * KB. Such ranges are suitable for the DMA masters that DMA between
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+ * the crypto SRAM (which is mapped through an I/O window) and a
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+ * device. This is the case for the crypto engines.
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+ */
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+
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static struct mbus_dram_target_info mvebu_mbus_dram_info;
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+static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
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+
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const struct mbus_dram_target_info *mv_mbus_dram_info(void)
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{
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return &mvebu_mbus_dram_info;
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}
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EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
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+const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
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+{
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+ return &mvebu_mbus_dram_info_nooverlap;
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+}
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+EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
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+
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/* Checks whether the given window has remap capability */
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static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
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const int win)
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@@ -323,8 +348,9 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
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ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
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(attr << WIN_CTRL_ATTR_SHIFT) |
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(target << WIN_CTRL_TGT_SHIFT) |
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- WIN_CTRL_SYNCBARRIER |
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WIN_CTRL_ENABLE;
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+ if (mbus->hw_io_coherency)
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+ ctrl |= WIN_CTRL_SYNCBARRIER;
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writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
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writel(ctrl, addr + WIN_CTRL_OFF);
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@@ -592,7 +618,7 @@ mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
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* This part of the memory is above 4 GB, so we don't
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* care for the MBus bridge hole.
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*/
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- if (r->base >= 0x100000000)
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+ if (r->base >= 0x100000000ULL)
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continue;
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/*
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@@ -604,49 +630,32 @@ mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
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}
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*start = s;
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- *end = 0x100000000;
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+ *end = 0x100000000ULL;
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}
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+/*
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+ * This function fills in the mvebu_mbus_dram_info_nooverlap data
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+ * structure, by looking at the mvebu_mbus_dram_info data, and
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+ * removing the parts of it that overlap with I/O windows.
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+ */
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static void __init
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-mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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+mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
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{
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- int i;
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- int cs;
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uint64_t mbus_bridge_base, mbus_bridge_end;
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-
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- mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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+ int cs_nooverlap = 0;
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+ int i;
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mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
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- for (i = 0, cs = 0; i < 4; i++) {
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- u64 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
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- u64 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
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- u64 end;
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+ for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
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struct mbus_dram_window *w;
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+ u64 base, size, end;
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- /* Ignore entries that are not enabled */
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- if (!(size & DDR_SIZE_ENABLED))
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- continue;
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-
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- /*
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- * Ignore entries whose base address is above 2^32,
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- * since devices cannot DMA to such high addresses
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- */
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- if (base & DDR_BASE_CS_HIGH_MASK)
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- continue;
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-
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- base = base & DDR_BASE_CS_LOW_MASK;
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- size = (size | ~DDR_SIZE_MASK) + 1;
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+ w = &mvebu_mbus_dram_info.cs[i];
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+ base = w->base;
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+ size = w->size;
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end = base + size;
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- /*
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- * Adjust base/size of the current CS to make sure it
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- * doesn't overlap with the MBus bridge hole. This is
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- * particularly important for devices that do DMA from
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- * DRAM to a SRAM mapped in a MBus window, such as the
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- * CESA cryptographic engine.
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- */
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-
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/*
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* The CS is fully enclosed inside the MBus bridge
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* area, so ignore it.
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@@ -670,7 +679,7 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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if (base < mbus_bridge_base && end > mbus_bridge_base)
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size -= end - mbus_bridge_base;
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- w = &mvebu_mbus_dram_info.cs[cs++];
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+ w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
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w->cs_index = i;
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w->mbus_attr = 0xf & ~(1 << i);
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if (mbus->hw_io_coherency)
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@@ -678,6 +687,42 @@ mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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w->base = base;
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w->size = size;
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}
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+
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+ mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
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+ mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
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+}
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+
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+static void __init
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+mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
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+{
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+ int i;
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+ int cs;
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+
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+ mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
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+
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+ for (i = 0, cs = 0; i < 4; i++) {
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+ u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
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+ u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
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+
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+ /*
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+ * We only take care of entries for which the chip
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+ * select is enabled, and that don't have high base
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+ * address bits set (devices can only access the first
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+ * 32 bits of the memory).
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+ */
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+ if ((size & DDR_SIZE_ENABLED) &&
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+ !(base & DDR_BASE_CS_HIGH_MASK)) {
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+ struct mbus_dram_window *w;
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+
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+ w = &mvebu_mbus_dram_info.cs[cs++];
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+ w->cs_index = i;
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+ w->mbus_attr = 0xf & ~(1 << i);
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+ if (mbus->hw_io_coherency)
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+ w->mbus_attr |= ATTR_HW_COHERENCY;
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+ w->base = base & DDR_BASE_CS_LOW_MASK;
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+ w->size = (size | ~DDR_SIZE_MASK) + 1;
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+ }
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+ }
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mvebu_mbus_dram_info.num_cs = cs;
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}
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@@ -1035,6 +1080,7 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
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mvebu_mbus_disable_window(mbus, win);
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mbus->soc->setup_cpu_target(mbus);
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+ mvebu_mbus_setup_cpu_target_nooverlap(mbus);
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if (is_coherent)
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writel(UNIT_SYNC_BARRIER_ALL,
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Arnd Bergmann