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altera tse: Error-Bit on tx-avalon-stream always set.

The Error-Bit on the avalon streaming interface of the
tx-dma-channel was always set. In SGMII configurations
this leads to error-symbols on the PCS and packet-rejection
on the receiver side (e.g. SGMII/1000Base-X connected switch).

This only applies to the tse-configuration with MSGDMA.

This issue was detected and fixed on a custom board with
a direct connection to a Marvell switch in SGMII-PHY-Mode.
(incl. custom patches for SGMII-PCS).

According to the datasheet if ff_tx_err (avalon-streaming)
is set it is forwarded to gm_tx_err. As a result the PCS
is forwarding the error by sending a "/V/"-caracter.

Signed-off-by: Andreas Oetken <ennoerlangen@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Andreas Oetken 10 years ago
parent
commit
71cd26e76a
1 changed files with 0 additions and 1 deletions
  1. 0 1
      drivers/net/ethernet/altera/altera_msgdmahw.h

+ 0 - 1
drivers/net/ethernet/altera/altera_msgdmahw.h

@@ -72,7 +72,6 @@ struct msgdma_extended_desc {
 #define MSGDMA_DESC_CTL_TX_SINGLE	(MSGDMA_DESC_CTL_GEN_SOP |	\
 #define MSGDMA_DESC_CTL_TX_SINGLE	(MSGDMA_DESC_CTL_GEN_SOP |	\
 					 MSGDMA_DESC_CTL_GEN_EOP |	\
 					 MSGDMA_DESC_CTL_GEN_EOP |	\
 					 MSGDMA_DESC_CTL_TR_COMP_IRQ |	\
 					 MSGDMA_DESC_CTL_TR_COMP_IRQ |	\
-					 MSGDMA_DESC_CTL_TR_ERR_IRQ |	\
 					 MSGDMA_DESC_CTL_GO)
 					 MSGDMA_DESC_CTL_GO)
 
 
 #define MSGDMA_DESC_CTL_RX_SINGLE	(MSGDMA_DESC_CTL_END_ON_EOP |	\
 #define MSGDMA_DESC_CTL_RX_SINGLE	(MSGDMA_DESC_CTL_END_ON_EOP |	\