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@@ -0,0 +1,88 @@
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+/*
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+ * Some portions derived from code covered by the following notice:
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+ *
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+ * Copyright (c) 2010-2013 Intel Corporation. All rights reserved.
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+ * All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions
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+ * are met:
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+ *
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in
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+ * the documentation and/or other materials provided with the
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+ * distribution.
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+ * * Neither the name of Intel Corporation nor the names of its
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+ * contributors may be used to endorse or promote products derived
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+ * from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ */
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+
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+#include <linux/hash.h>
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+
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+#include <asm/processor.h>
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+#include <asm/cpufeature.h>
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+#include <asm/hash.h>
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+
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+static inline u32 crc32_u32(u32 crc, u32 val)
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+{
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+ asm ("crc32l %1,%0\n" : "+r" (crc) : "rm" (val));
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+ return crc;
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+}
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+
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+static u32 intel_crc4_2_hash(const void *data, u32 len, u32 seed)
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+{
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+ const u32 *p32 = (const u32 *) data;
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+ u32 i, tmp = 0;
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+
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+ for (i = 0; i < len / 4; i++)
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+ seed = crc32_u32(*p32++, seed);
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+
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+ switch (3 - (len & 0x03)) {
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+ case 0:
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+ tmp |= *((const u8 *) p32 + 2) << 16;
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+ /* fallthrough */
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+ case 1:
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+ tmp |= *((const u8 *) p32 + 1) << 8;
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+ /* fallthrough */
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+ case 2:
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+ tmp |= *((const u8 *) p32);
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+ seed = crc32_u32(tmp, seed);
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+ default:
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+ break;
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+ }
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+
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+ return seed;
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+}
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+
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+static u32 intel_crc4_2_hash2(const u32 *data, u32 len, u32 seed)
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+{
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+ const u32 *p32 = (const u32 *) data;
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+ u32 i;
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+
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+ for (i = 0; i < len; i++)
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+ seed = crc32_u32(*p32++, seed);
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+
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+ return seed;
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+}
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+
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+void setup_arch_fast_hash(struct fast_hash_ops *ops)
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+{
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+ if (cpu_has_xmm4_2) {
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+ ops->hash = intel_crc4_2_hash;
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+ ops->hash2 = intel_crc4_2_hash2;
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+ }
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+}
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