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@@ -223,7 +223,8 @@ enum {
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FAULT_AND_CONTINUE /* Unsupported */
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};
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#define GEN8_CTX_ID_SHIFT 32
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-#define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
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+#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
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+#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
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static int intel_lr_context_pin(struct intel_context *ctx,
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struct intel_engine_cs *engine);
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@@ -2317,6 +2318,27 @@ make_rpcs(struct drm_device *dev)
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return rpcs;
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}
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+static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *ring)
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+{
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+ u32 indirect_ctx_offset;
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+
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+ switch (INTEL_INFO(ring->dev)->gen) {
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+ default:
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+ MISSING_CASE(INTEL_INFO(ring->dev)->gen);
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+ /* fall through */
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+ case 9:
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+ indirect_ctx_offset =
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+ GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
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+ break;
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+ case 8:
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+ indirect_ctx_offset =
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+ GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
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+ break;
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+ }
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+
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+ return indirect_ctx_offset;
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+}
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+
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static int
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populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj,
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struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf)
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@@ -2389,7 +2411,7 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
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(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
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reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
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- CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6;
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+ intel_lr_indirect_ctx_offset(ring) << 6;
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reg_state[CTX_BB_PER_CTX_PTR+1] =
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(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
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