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@@ -0,0 +1,86 @@
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+/*
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+ * VFIO platform driver specialized for Calxeda xgmac reset
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+ * reset code is inherited from calxeda xgmac native driver
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+ *
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+ * Copyright 2010-2011 Calxeda, Inc.
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+ * Copyright (c) 2015 Linaro Ltd.
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+ * www.linaro.org
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along with
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+ * this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+
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+#include "vfio_platform_private.h"
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+
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+#define DRIVER_VERSION "0.1"
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+#define DRIVER_AUTHOR "Eric Auger <eric.auger@linaro.org>"
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+#define DRIVER_DESC "Reset support for Calxeda xgmac vfio platform device"
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+
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+#define CALXEDAXGMAC_COMPAT "calxeda,hb-xgmac"
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+
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+/* XGMAC Register definitions */
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+#define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
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+
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+/* DMA Control and Status Registers */
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+#define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */
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+#define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */
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+
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+/* DMA Control registe defines */
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+#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
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+#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
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+
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+/* Common MAC defines */
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+#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
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+#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
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+
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+static inline void xgmac_mac_disable(void __iomem *ioaddr)
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+{
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+ u32 value = readl(ioaddr + XGMAC_DMA_CONTROL);
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+
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+ value &= ~(DMA_CONTROL_ST | DMA_CONTROL_SR);
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+ writel(value, ioaddr + XGMAC_DMA_CONTROL);
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+
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+ value = readl(ioaddr + XGMAC_CONTROL);
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+ value &= ~(MAC_ENABLE_TX | MAC_ENABLE_RX);
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+ writel(value, ioaddr + XGMAC_CONTROL);
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+}
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+
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+int vfio_platform_calxedaxgmac_reset(struct vfio_platform_device *vdev)
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+{
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+ struct vfio_platform_region reg = vdev->regions[0];
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+
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+ if (!reg.ioaddr) {
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+ reg.ioaddr =
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+ ioremap_nocache(reg.addr, reg.size);
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+ if (!reg.ioaddr)
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+ return -ENOMEM;
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+ }
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+
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+ /* disable IRQ */
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+ writel(0, reg.ioaddr + XGMAC_DMA_INTR_ENA);
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+
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+ /* Disable the MAC core */
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+ xgmac_mac_disable(reg.ioaddr);
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(vfio_platform_calxedaxgmac_reset);
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+
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+MODULE_VERSION(DRIVER_VERSION);
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+MODULE_LICENSE("GPL v2");
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+MODULE_AUTHOR(DRIVER_AUTHOR);
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+MODULE_DESCRIPTION(DRIVER_DESC);
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