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@@ -168,6 +168,8 @@
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#define IB_ATC_EN (1U << 23)
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#define IB_ATC_EN (1U << 23)
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#define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)
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#define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)
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+#define AQL_ENABLE 1
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+
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#define CP_HQD_DEQUEUE_REQUEST 0xC974
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#define CP_HQD_DEQUEUE_REQUEST 0xC974
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#define DEQUEUE_REQUEST_DRAIN 1
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#define DEQUEUE_REQUEST_DRAIN 1
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#define DEQUEUE_REQUEST_RESET 2
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#define DEQUEUE_REQUEST_RESET 2
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@@ -188,6 +190,17 @@
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#define MQD_VMID_MASK (0xf << 0)
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#define MQD_VMID_MASK (0xf << 0)
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#define MQD_CONTROL_PRIV_STATE_EN (1U << 8)
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#define MQD_CONTROL_PRIV_STATE_EN (1U << 8)
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+#define SDMA_RB_VMID(x) (x << 24)
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+#define SDMA_RB_ENABLE (1 << 0)
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+#define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */
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+#define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
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+#define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
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+#define SDMA_OFFSET(x) (x << 0)
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+#define SDMA_DB_ENABLE (1 << 28)
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+#define SDMA_ATC (1 << 0)
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+#define SDMA_VA_PTR32 (1 << 4)
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+#define SDMA_VA_SHARED_BASE(x) (x << 8)
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+
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#define GRBM_GFX_INDEX 0x30800
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#define GRBM_GFX_INDEX 0x30800
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#define INSTANCE_INDEX(x) ((x) << 0)
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#define INSTANCE_INDEX(x) ((x) << 0)
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#define SH_INDEX(x) ((x) << 8)
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#define SH_INDEX(x) ((x) << 8)
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