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@@ -18,10 +18,12 @@
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* 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
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* 0c08: Xeon E3-1200 v3 Processor DRAM Controller
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* 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
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+ * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
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*
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* Based on Intel specification:
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* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
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* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
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+ * http://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
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*
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* According to the above datasheet (p.16):
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* "
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@@ -57,6 +59,7 @@
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
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+#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
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#define IE31200_DIMMS 4
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#define IE31200_RANKS 8
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@@ -376,7 +379,12 @@ static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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void __iomem *window;
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struct ie31200_priv *priv;
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u32 addr_decode, mad_offset;
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- bool skl = (pdev->device == PCI_DEVICE_ID_INTEL_IE31200_HB_8);
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+
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+ /*
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+ * Kaby Lake seems to work like Skylake. Please re-visit this logic
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+ * when adding new CPU support.
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+ */
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+ bool skl = (pdev->device >= PCI_DEVICE_ID_INTEL_IE31200_HB_8);
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edac_dbg(0, "MC:\n");
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@@ -559,6 +567,9 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
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{
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PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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IE31200},
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+ {
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+ PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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+ IE31200},
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{
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0,
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} /* 0 terminated list. */
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