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@@ -52,6 +52,12 @@
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#define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
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#define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
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+#define CVMX_SSO_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000001000ull))
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+#define CVMX_SSO_WQ_IQ_DIS (CVMX_ADD_IO_SEG(0x0001670000001010ull))
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+#define CVMX_SSO_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000001020ull))
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+#define CVMX_SSO_PPX_GRP_MSK(offset) (CVMX_ADD_IO_SEG(0x0001670000006000ull) + ((offset) & 31) * 8)
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+#define CVMX_SSO_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000007000ull) + ((offset) & 63) * 8)
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+
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union cvmx_pow_bist_stat {
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uint64_t u64;
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struct cvmx_pow_bist_stat_s {
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@@ -1286,4 +1292,27 @@ union cvmx_pow_ws_pcx {
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struct cvmx_pow_ws_pcx_s cnf71xx;
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};
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+union cvmx_sso_wq_int_thrx {
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+ uint64_t u64;
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+ struct {
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+#ifdef __BIG_ENDIAN_BITFIELD
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+ uint64_t reserved_33_63:31;
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+ uint64_t tc_en:1;
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+ uint64_t tc_thr:4;
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+ uint64_t reserved_26_27:2;
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+ uint64_t ds_thr:12;
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+ uint64_t reserved_12_13:2;
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+ uint64_t iq_thr:12;
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+#else
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+ uint64_t iq_thr:12;
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+ uint64_t reserved_12_13:2;
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+ uint64_t ds_thr:12;
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+ uint64_t reserved_26_27:2;
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+ uint64_t tc_thr:4;
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+ uint64_t tc_en:1;
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+ uint64_t reserved_33_63:31;
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+#endif
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+ } s;
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+};
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+
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#endif
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