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@@ -1188,6 +1188,7 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
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static int bxt_init_workarounds(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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+ u32 val;
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int ret;
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ret = gen9_init_workarounds(engine);
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@@ -1199,29 +1200,23 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
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STALL_DOP_GATING_DISABLE);
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/* WaDisablePooledEuLoadBalancingFix:bxt */
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- if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
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- I915_WRITE(FF_SLICE_CS_CHICKEN2,
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- _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
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- }
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+ I915_WRITE(FF_SLICE_CS_CHICKEN2,
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+ _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
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/* WaProgramL3SqcReg1DefaultForPerf:bxt */
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- if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
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- u32 val = I915_READ(GEN8_L3SQCREG1);
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- val &= ~L3_PRIO_CREDITS_MASK;
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- val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
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- I915_WRITE(GEN8_L3SQCREG1, val);
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- }
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+ val = I915_READ(GEN8_L3SQCREG1);
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+ val &= ~L3_PRIO_CREDITS_MASK;
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+ val |= L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2);
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+ I915_WRITE(GEN8_L3SQCREG1, val);
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/* WaToEnableHwFixForPushConstHWBug:bxt */
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- if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
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- WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
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- GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
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+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
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+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
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/* WaInPlaceDecompressionHang:bxt */
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- if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
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- I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
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- (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
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- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
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+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
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+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
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+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
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return 0;
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}
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