|
@@ -36,8 +36,8 @@
|
|
|
#define PCIE_CAP_OFFSET 0x100
|
|
|
|
|
|
/* Quirks for the listed devices */
|
|
|
-#define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190
|
|
|
-#define PCI_DEVICE_ID_INTEL_MRFL_HSU 0x1191
|
|
|
+#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
|
|
|
+#define PCI_DEVICE_ID_INTEL_MRFLD_HSU 0x1191
|
|
|
|
|
|
/* Fixed BAR fields */
|
|
|
#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
|
|
@@ -229,7 +229,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
|
|
|
* Skip HS UART common registers device since it has
|
|
|
* IRQ0 assigned and not used by the kernel.
|
|
|
*/
|
|
|
- if (dev->device == PCI_DEVICE_ID_INTEL_MRFL_HSU)
|
|
|
+ if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU)
|
|
|
return -EBUSY;
|
|
|
/*
|
|
|
* TNG has IRQ0 assigned to eMMC controller. But there
|
|
@@ -238,7 +238,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
|
|
|
* eMMC gets it. The rest of devices still could be
|
|
|
* enabled without interrupt line being allocated.
|
|
|
*/
|
|
|
- if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
|
|
|
+ if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC)
|
|
|
return 0;
|
|
|
}
|
|
|
break;
|