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@@ -62,9 +62,11 @@
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#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
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#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
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-/* The Armada XP has per-CPU registers for interrupt cause, interrupt
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+/*
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+ * The Armada XP has per-CPU registers for interrupt cause, interrupt
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* mask and interrupt level mask. Those are relative to the
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- * percpu_membase. */
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+ * percpu_membase.
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+ */
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#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
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#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
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#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
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@@ -239,8 +241,10 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
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int ret;
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u32 u;
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- /* Check with the pinctrl driver whether this pin is usable as
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- * an input GPIO */
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+ /*
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+ * Check with the pinctrl driver whether this pin is usable as
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+ * an input GPIO
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+ */
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ret = pinctrl_gpio_direction_input(chip->base + pin);
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if (ret)
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return ret;
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@@ -262,8 +266,10 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
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int ret;
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u32 u;
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- /* Check with the pinctrl driver whether this pin is usable as
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- * an output GPIO */
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+ /*
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+ * Check with the pinctrl driver whether this pin is usable as
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+ * an output GPIO
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+ */
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ret = pinctrl_gpio_direction_output(chip->base + pin);
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if (ret)
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return ret;
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@@ -712,8 +718,10 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
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if (IS_ERR(mvchip->membase))
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return PTR_ERR(mvchip->membase);
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- /* The Armada XP has a second range of registers for the
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- * per-CPU registers */
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+ /*
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+ * The Armada XP has a second range of registers for the
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+ * per-CPU registers
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+ */
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if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
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