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@@ -403,6 +403,15 @@ void amdgpu_pci_config_reset(struct amdgpu_device *adev)
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*/
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static int amdgpu_doorbell_init(struct amdgpu_device *adev)
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{
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+ /* No doorbell on SI hardware generation */
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+ if (adev->asic_type < CHIP_BONAIRE) {
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+ adev->doorbell.base = 0;
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+ adev->doorbell.size = 0;
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+ adev->doorbell.num_doorbells = 0;
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+ adev->doorbell.ptr = NULL;
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+ return 0;
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+ }
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+
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/* doorbell bar mapping */
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adev->doorbell.base = pci_resource_start(adev->pdev, 2);
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adev->doorbell.size = pci_resource_len(adev->pdev, 2);
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@@ -2075,9 +2084,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
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DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
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- if (adev->asic_type >= CHIP_BONAIRE)
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- /* doorbell bar mapping */
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- amdgpu_doorbell_init(adev);
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+ /* doorbell bar mapping */
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+ amdgpu_doorbell_init(adev);
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/* io port mapping */
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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@@ -2304,8 +2312,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
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adev->rio_mem = NULL;
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iounmap(adev->rmmio);
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adev->rmmio = NULL;
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- if (adev->asic_type >= CHIP_BONAIRE)
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- amdgpu_doorbell_fini(adev);
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+ amdgpu_doorbell_fini(adev);
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amdgpu_debugfs_regs_cleanup(adev);
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}
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