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@@ -1753,7 +1753,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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if (pll != ATOM_PPLL_INVALID)
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if (pll != ATOM_PPLL_INVALID)
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return pll;
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return pll;
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}
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}
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- } else {
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+ } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */
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/* use the same PPLL for all monitors with the same clock */
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/* use the same PPLL for all monitors with the same clock */
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pll = radeon_get_shared_nondp_ppll(crtc);
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pll = radeon_get_shared_nondp_ppll(crtc);
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if (pll != ATOM_PPLL_INVALID)
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if (pll != ATOM_PPLL_INVALID)
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