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@@ -39,6 +39,7 @@
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static u32 pit_cycle; /* write-once */
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static u32 pit_cnt; /* access only w/system irq blocked */
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static void __iomem *pit_base_addr __read_mostly;
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+static struct clk *mck;
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static inline unsigned int pit_read(unsigned int reg_offset)
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{
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@@ -195,10 +196,14 @@ static int __init of_at91sam926x_pit_init(void)
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if (!pit_base_addr)
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goto node_err;
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+ mck = of_clk_get(np, 0);
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+
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/* Get the interrupts property */
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ret = irq_of_parse_and_map(np, 0);
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if (!ret) {
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pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
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+ if (!IS_ERR(mck))
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+ clk_put(mck);
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goto ioremap_err;
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}
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at91sam926x_pit_irq.irq = ret;
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@@ -230,6 +235,8 @@ void __init at91sam926x_pit_init(void)
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unsigned bits;
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int ret;
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+ mck = ERR_PTR(-ENOENT);
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+
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/* For device tree enabled device: initialize here */
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of_at91sam926x_pit_init();
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@@ -237,7 +244,12 @@ void __init at91sam926x_pit_init(void)
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* Use our actual MCK to figure out how many MCK/16 ticks per
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* 1/HZ period (instead of a compile-time constant LATCH).
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*/
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- pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
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+ if (IS_ERR(mck))
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+ mck = clk_get(NULL, "mck");
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+
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+ if (IS_ERR(mck))
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+ panic("AT91: PIT: Unable to get mck clk\n");
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+ pit_rate = clk_get_rate(mck) / 16;
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pit_cycle = (pit_rate + HZ/2) / HZ;
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WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);
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