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@@ -25,10 +25,48 @@
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#define __AMDGPU_IH_H__
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struct amdgpu_device;
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+ /*
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+ * vega10+ IH clients
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+ */
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+enum amdgpu_ih_clientid
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+{
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+ AMDGPU_IH_CLIENTID_IH = 0x00,
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+ AMDGPU_IH_CLIENTID_ACP = 0x01,
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+ AMDGPU_IH_CLIENTID_ATHUB = 0x02,
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+ AMDGPU_IH_CLIENTID_BIF = 0x03,
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+ AMDGPU_IH_CLIENTID_DCE = 0x04,
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+ AMDGPU_IH_CLIENTID_ISP = 0x05,
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+ AMDGPU_IH_CLIENTID_PCIE0 = 0x06,
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+ AMDGPU_IH_CLIENTID_RLC = 0x07,
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+ AMDGPU_IH_CLIENTID_SDMA0 = 0x08,
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+ AMDGPU_IH_CLIENTID_SDMA1 = 0x09,
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+ AMDGPU_IH_CLIENTID_SE0SH = 0x0a,
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+ AMDGPU_IH_CLIENTID_SE1SH = 0x0b,
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+ AMDGPU_IH_CLIENTID_SE2SH = 0x0c,
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+ AMDGPU_IH_CLIENTID_SE3SH = 0x0d,
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+ AMDGPU_IH_CLIENTID_SYSHUB = 0x0e,
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+ AMDGPU_IH_CLIENTID_THM = 0x0f,
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+ AMDGPU_IH_CLIENTID_UVD = 0x10,
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+ AMDGPU_IH_CLIENTID_VCE0 = 0x11,
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+ AMDGPU_IH_CLIENTID_VMC = 0x12,
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+ AMDGPU_IH_CLIENTID_XDMA = 0x13,
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+ AMDGPU_IH_CLIENTID_GRBM_CP = 0x14,
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+ AMDGPU_IH_CLIENTID_ATS = 0x15,
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+ AMDGPU_IH_CLIENTID_ROM_SMUIO = 0x16,
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+ AMDGPU_IH_CLIENTID_DF = 0x17,
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+ AMDGPU_IH_CLIENTID_VCE1 = 0x18,
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+ AMDGPU_IH_CLIENTID_PWR = 0x19,
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+ AMDGPU_IH_CLIENTID_UTCL2 = 0x1b,
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+ AMDGPU_IH_CLIENTID_EA = 0x1c,
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+ AMDGPU_IH_CLIENTID_UTCL2LOG = 0x1d,
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+ AMDGPU_IH_CLIENTID_MP0 = 0x1e,
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+ AMDGPU_IH_CLIENTID_MP1 = 0x1f,
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-#define AMDGPU_IH_CLIENTID_LEGACY 0
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+ AMDGPU_IH_CLIENTID_MAX
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-#define AMDGPU_IH_CLIENTID_MAX 0x1f
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+};
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+
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+#define AMDGPU_IH_CLIENTID_LEGACY 0
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/*
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* R6xx+ IH ring
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