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@@ -10,6 +10,8 @@
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#include <asm/special_insns.h>
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#include <asm/smp.h>
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#include <asm/invpcid.h>
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+#include <asm/pti.h>
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+#include <asm/processor-flags.h>
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static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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{
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@@ -24,24 +26,54 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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/* There are 12 bits of space for ASIDS in CR3 */
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#define CR3_HW_ASID_BITS 12
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+
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/*
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* When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
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* user/kernel switches
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*/
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-#define PTI_CONSUMED_ASID_BITS 0
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+#ifdef CONFIG_PAGE_TABLE_ISOLATION
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+# define PTI_CONSUMED_PCID_BITS 1
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+#else
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+# define PTI_CONSUMED_PCID_BITS 0
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+#endif
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+
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+#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
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-#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS - PTI_CONSUMED_ASID_BITS)
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/*
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* ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
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* for them being zero-based. Another -1 is because ASID 0 is reserved for
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* use by non-PCID-aware users.
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*/
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-#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_ASID_BITS) - 2)
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+#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
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+
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+/*
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+ * 6 because 6 should be plenty and struct tlb_state will fit in two cache
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+ * lines.
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+ */
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+#define TLB_NR_DYN_ASIDS 6
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static inline u16 kern_pcid(u16 asid)
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{
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VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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+
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+#ifdef CONFIG_PAGE_TABLE_ISOLATION
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+ /*
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+ * Make sure that the dynamic ASID space does not confict with the
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+ * bit we are using to switch between user and kernel ASIDs.
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+ */
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+ BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_SWITCH_BIT));
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+
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/*
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+ * The ASID being passed in here should have respected the
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+ * MAX_ASID_AVAILABLE and thus never have the switch bit set.
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+ */
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+ VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_SWITCH_BIT));
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+#endif
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+ /*
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+ * The dynamically-assigned ASIDs that get passed in are small
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+ * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
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+ * so do not bother to clear it.
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+ *
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* If PCID is on, ASID-aware code paths put the ASID+1 into the
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* PCID bits. This serves two purposes. It prevents a nasty
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* situation in which PCID-unaware code saves CR3, loads some other
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@@ -95,12 +127,6 @@ static inline bool tlb_defer_switch_to_init_mm(void)
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return !static_cpu_has(X86_FEATURE_PCID);
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}
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-/*
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- * 6 because 6 should be plenty and struct tlb_state will fit in
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- * two cache lines.
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- */
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-#define TLB_NR_DYN_ASIDS 6
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-
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struct tlb_context {
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u64 ctx_id;
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u64 tlb_gen;
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@@ -145,6 +171,13 @@ struct tlb_state {
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*/
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bool invalidate_other;
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+ /*
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+ * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate
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+ * the corresponding user PCID needs a flush next time we
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+ * switch to it; see SWITCH_TO_USER_CR3.
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+ */
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+ unsigned short user_pcid_flush_mask;
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+
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/*
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* Access to this CR4 shadow and to H/W CR4 is protected by
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* disabling interrupts when modifying either one.
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@@ -249,15 +282,42 @@ static inline void cr4_set_bits_and_update_boot(unsigned long mask)
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extern void initialize_tlbstate_and_flush(void);
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+/*
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+ * Given an ASID, flush the corresponding user ASID. We can delay this
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+ * until the next time we switch to it.
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+ *
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+ * See SWITCH_TO_USER_CR3.
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+ */
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+static inline void invalidate_user_asid(u16 asid)
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+{
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+ /* There is no user ASID if address space separation is off */
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+ if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
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+ return;
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+
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+ /*
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+ * We only have a single ASID if PCID is off and the CR3
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+ * write will have flushed it.
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+ */
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+ if (!cpu_feature_enabled(X86_FEATURE_PCID))
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+ return;
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+
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+ if (!static_cpu_has(X86_FEATURE_PTI))
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+ return;
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+
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+ __set_bit(kern_pcid(asid),
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+ (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
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+}
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+
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/*
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* flush the entire current user mapping
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*/
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static inline void __native_flush_tlb(void)
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{
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+ invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
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/*
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- * If current->mm == NULL then we borrow a mm which may change during a
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- * task switch and therefore we must not be preempted while we write CR3
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- * back:
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+ * If current->mm == NULL then we borrow a mm which may change
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+ * during a task switch and therefore we must not be preempted
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+ * while we write CR3 back:
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*/
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preempt_disable();
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native_write_cr3(__native_read_cr3());
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@@ -301,7 +361,14 @@ static inline void __native_flush_tlb_global(void)
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*/
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static inline void __native_flush_tlb_single(unsigned long addr)
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{
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+ u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
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+
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asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
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+
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+ if (!static_cpu_has(X86_FEATURE_PTI))
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+ return;
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+
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+ invalidate_user_asid(loaded_mm_asid);
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}
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/*
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Peter Zijlstra