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@@ -6256,7 +6256,7 @@ static void si_parse_pplib_clock_info(struct radeon_device *rdev,
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if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
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index == 0) {
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/* XXX disable for A0 tahiti */
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- si_pi->ulv.supported = true;
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+ si_pi->ulv.supported = false;
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si_pi->ulv.pl = *pl;
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si_pi->ulv.one_pcie_lane_in_ulv = false;
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si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
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